ISL6312A_15 Datasheet, PDF(31/36 Page) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10,VR11, and AMD Applications

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ISL6312A_15 Datasheet, PDF (31/36 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10,VR11, and AMD Applications

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ISL6312A

Case 1:

---------------1----------------

2ïï°ï LïC

RC = RFB ï 2-----ï---ï°-----ï---f-0-0--.--6ï---6V-----Pï---V---P--I--N-ï-------L-----ï---C---

CC = 2-----ï---ï°-----ï-0--V-.--6-P--6--P---ï--ï-V--R--I--N-F---B-----ï----f-0--

Case 2:

---------------1----------------

2ïï°ï LïC

ï£

2-----ï---ï°-----ï---C--1----ï---E----S-----R---

RC = RFB ï V-----P------P-----ï---ï¨--02---.--6ï---ï°6----ï©-ï-2---V--ï---I-f-N-0--2----ï----L-----ï---C--

CC = ï¨---2-----ï---ï°----ï©--2----ï----f--0---2-0---ï.--6--V-6---P--ï----PV-----Iï-N--R-----F---B-----ï-------L-----ï---C---

(EQ. 44)

Case 3:

f0 > 2-----ï---ï°-----ï---C--1----ï---E----S-----R---

RC = RFB ï 2-0----.ï-6--ï°--6----ï-ï--f--V0----Iï--N-V----ïP---E----P-S----ï-R--L-

-----0----.-6----6----ï---V-----I-N------ï---E----S-----R-----ï--------C-------

2 ï ï° ï VP-P ï RFB ï f0 ï L

In Equation 44, L is the per-channel filter inductance divided

by the number of active channels; C is the sum total of all

output capacitors; ESR is the equivalent series resistance of

the bulk output filter capacitance; and VP-P is the

peak-to-peak sawtooth signal amplitude as described in the

âElectrical Specificationsâ on page 7.

Once selected, the compensation values in Equation 44

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

improved by making adjustments to RC. Slowly increase the

value of RC while observing the transient performance on an

oscilloscope until no further improvement is noted. Normally,

CC will not need adjustment. Keep the value of CC from

Equation 44 unless some performance issue is noted.

The optional capacitor C2, is sometimes needed to bypass

noise away from the PWM comparator (see Figure 20).

Keep a position available for C2, and be prepared to install a

high frequency capacitor of between 22pF and 150pF in

case any leading edge jitter problem is noted.

Output Filter Design

The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter limits the system

transient response. The output capacitors must supply or

sink load current while the current in the output inductors

increases or decreases to meet the demand.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit.

Output filter design begins with minimizing the cost of this part

of the circuit. The critical load parameters in choosing the

output capacitors are the maximum size of the load step, ïI,

the load-current slew rate, di/dt, and the maximum allowable

output voltage deviation under transient loading, ïVMAX.

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

initially deviate by an amount approximated by the voltage

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the load

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total output

voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by showing an

amount on Equation 45:

ïV ï» ESL ï d-d---ti + ESR ï ïI

(EQ. 45)

The filter capacitor must have sufficiently low ESL and ESR

so that ïV < ïVMAX.

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited high

frequency performance. Minimizing the ESL of the high

frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

The ESR of the bulk capacitors also creates the majority of

the output voltage ripple. As the bulk capacitors sink and

source the inductor AC ripple current (see âInterleavingâ on

page 11 and Equation 2), a voltage develops across the bulk

capacitor ESR equal to IC,PP (ESR). Thus, once the output

capacitors are selected, the maximum allowable ripple

voltage, VPP(MAX), determines the lower limit on the

inductance.

(EQ. 46)

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

ïVMAX. This places an upper limit on inductance.

Equation 47 gives the upper limit on L for the cases, when

the trailing edge of the current transient causes a greater

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FN9290.6

January 22, 2015

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