ISL6312A_15 Datasheet, PDF (22/36 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10,VR11, and AMD Applications

ISL6312A
In order to ensure the smooth transition of output voltage
during an AMD VID change, a VID step change smoothing
network is required. This network is composed of an internal
1k resistor between the DAC and the REF pin, and the
external capacitor C_REF, between the REF pin and ground.
For AMD VID transitions C_REF should be a 1000pF capacitor.
User Selectable Adaptive Deadtime Control
Techniques
The ISL6312A integrated drivers incorporate two different
adaptive deadtime control techniques, which the user can
choose between. Both of these control techniques help to
minimize deadtime, resulting in high efficiency from the
reduced freewheeling time of the lower MOSFET body-diode
conduction, and both help to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other
has turned off.
The difference between the two adaptive deadtime control
techniques is the method in which they detect that the lower
MOSFET has transitioned off in order to turn on the upper
MOSFET. The state of the DRSEL pin chooses, which of the
two control techniques is active. By tying the DRSEL pin
directly to ground, the PHASE Detect Scheme is chosen,
which monitors the voltage on the PHASE pin to determine if
the lower MOSFET has transitioned off or not. Tying the
DRSEL pin to VCC though a 50k resistor selects the
LGATE Detect Scheme, which monitors the voltage on the
LGATE pin to determine if the lower MOSFET has turned off
or not. For both schemes, the method for determining
whether the upper MOSFET has transitioned off in order to
signal to turn on the lower MOSFET is the same.
PHASE DETECT
If the DRSEL pin is tied directly to ground, the PHASE Detect
adaptive deadtime control technique is selected. For the
PHASE detect scheme, during turn-off of the lower MOSFET,
the PHASE voltage is monitored until it reaches a -0.3V to
+0.8V (forward/reverse inductor current). At this time the
UGATE is released to rise. An auto-zero comparator is used to
correct the r_DS(ON) drop in the phase voltage preventing false
detection of the -0.3V phase level during r_DS(ON) conduction
period. In the case of zero current, the UGATE is released after
35ns delay of the LGATE dropping below 0.5V. When LGATE
first begins to transition low, this quick transition can disturb the
PHASE node and cause a false trip, so there is 20ns of
blanking time once LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
LGATE DETECT
If the DRSEL pin is tied to VCC through a 50k resistor, the
LGATE Detect adaptive deadtime control technique is selected.
For the LGATE detect scheme, during turn-off of the lower
MOSFET, the LGATE voltage is monitored until it reaches
1.75V. At this time the UGATE is released to rise.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V_{BOOT_CAP} (V)
FIGURE 9. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 16:
C_{BOOT_CAP}  _-----_V----_B-^Q---_O--^G--_O--^A---_T-^T--_{_}-^E--_C----_A----_P-
(EQ. 16)
Q_GATE= ^Q-----^G-----¹_V----^_G---^P--_S---^V-₁---^C-----^C---  N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The V_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive.
22
Submit Document Feedback
FN9290.6
January 22, 2015