ISL6312A_15 Datasheet, PDF (14/36 Pages) Intersil Corporation – Four-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR10,VR11, and AMD Applications

ISL6312A
V_Cs
=
--------------^---^D---s-------^C---------^LR---------+-----¹---^---------------


s


_--R-R_----11----+-_---R_-R---2-2---

C
+
1


K

DCR

I_L
(EQ. 5)
K = _R-----₂--^R---+--²--_R-----₁-
(EQ. 6)
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time
constant, then V_C is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1.
The capacitor voltage V_C, is then replicated across the
sense resistor R_ISEN. The current through R_ISEN is
proportional to the inductor current. Equation 7 shows that
the proportion between the channel current and the sensed
current (I_SEN) is driven by the value of the sense resistor,
the resistor divider ratio, and the DCR of the inductor.
I_SEN = K  I_L  _R---^D--_I--_S^C----_E-^R---_N--
(EQ. 7)
Output Voltage Setting
The ISL6312A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel
modes of operation, each VID pin is pulled up to an internal
1.2V voltage by a weak current source (40µA), which
decreases to 0A as the voltage at the VID pin varies from 0
to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a weak 20µA
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
The ISL6312A accommodates four different DAC ranges:
Intel VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and
AMD 6-bit. The state of the VRSEL and VID7 pins decide
which DAC version is active. Refer to Table 1 for a description
of how to select the desired DAC version. For VR11 setting,
tie the VRSEL pin to the midpoint of a 10k(or other suitable
value) resistor divider connected from VCC to GND.
TABLE 1. ISL6312A DAC SELECT TABLE
DAC VERSION
VRSEL PIN
VID7 PIN
VR10 (Extended)
VRSEL = GND
-
VR11
VRSEL = VCC/2
-
AMD 5-Bit
VRSEL = VCC
LOW
AMD 6-Bit
VRSEL = VCC
HIGH
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES
VID4 VID3 VID2 VID1 VID0 VID5 VID6 VDAC
0
1
0
1
0
1
1 1.60000
0
1
0
1
0
1
0 1.59375
0
1
0
1
1
0
1 1.58750
0
1
0
1
1
0
0 1.58125
0
1
0
1
1
1
1 1.57500
0
1
0
1
1
1
0 1.56875
0
1
1
0
0
0
1 1.56250
0
1
1
0
0
0
0 1.55625
0
1
1
0
0
1
1 1.55000
0
1
1
0
0
1
0 1.54375
0
1
1
0
1
0
1 1.53750
0
1
1
0
1
0
0 1.53125
0
1
1
0
1
1
1 1.52500
0
1
1
0
1
1
0 1.51875
0
1
1
1
0
0
1 1.51250
0
1
1
1
0
0
0 1.50625
0
1
1
1
0
1
1 1.50000
0
1
1
1
0
1
0 1.49375
0
1
1
1
1
0
1 1.48750
0
1
1
1
1
0
0 1.48125
0
1
1
1
1
1
1 1.47500
0
1
1
1
1
1
0 1.46875
1
0
0
0
0
0
1 1.46250
1
0
0
0
0
0
0 1.45625
1
0
0
0
0
1
1 1.45000
1
0
0
0
0
1
0 1.44375
1
0
0
0
1
0
1 1.43750
1
0
0
0
1
0
0 1.43125
1
0
0
0
1
1
1 1.42500
1
0
0
0
1
1
0 1.41875
1
0
0
1
0
0
1 1.41250
1
0
0
1
0
0
0 1.40625
1
0
0
1
0
1
1 1.40000
1
0
0
1
0
1
0 1.39375
1
0
0
1
1
0
1 1.38750
1
0
0
1
1
0
0 1.38125
1
0
0
1
1
1
1 1.37500
1
0
0
1
1
1
0 1.36875
1
0
1
0
0
0
1 1.36250
14
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FN9290.6
January 22, 2015