ISL68200 Datasheet, PDF (30/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller with Integrated Driver

ISL68200
TABLE 12. DESIGN AND LAYOUT CHECKLIST (Continued)
PIN
NOISE
NAME SENSITIVITY
DESCRIPTION
NTC
Yes Place NTC 10k (Murata, NCP15XH103J03RC,
 = 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET side
(see Figure 19); the return trace should be 20
mils away from other traces. Place 1.54kΩ
pull-up and decoupling capacitor (typically
0.1µF) in close proximity to the controller. The
pull-up resistor should be exactly tied to the
same point as VCC pin, not through an RC filter.
If not used, connect this pin to VCC.
IOUT
Yes Scale R such that IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant
of RC should be sufficient as an averaging
function for the digital I_OUT. An external pull-up
resistor to VCC is recommended cancel I_OUT
offset at 0A load. See “I_OUT Calibration” on
page 19
PROG1-4
No
Resistor divider must be referenced to VCC pin
and the system ground; they can be placed
anywhere. DO NOT use decoupling capacitors
on these pins.
GND
Yes Directly connect to low noise area of the
system ground. The GND PAD should use at
least 4 vias. Separate analog ground and
power ground with a 0Ω resistor is highly NOT
recommended.
LGATE
No
Low-side driver output and short and wide
trace in between this pin and MOSFET gate pin
as possible. High dV/dt signals should not be
close to any sensitive signals.
UGATE
No
High-side driver output and short and wide
trace in between this pin and MOSFET gate pin
as possible. High dV/dt signals should not be
close to any sensitive signals.
BOOT,
PHASE
Yes Place X7R 0.1µF or 0.22µF in proximity to
BOOT and PHASE pins. High dV/dt signals
should not be close to any sensitive signals.
PVCC
Yes Place X7R 4.7µF in proximity to PVCC pin and
the system ground plane.
TABLE 13. TOP LAYOUT TIPS
#
DESCRIPTION
1 The layer next to controller (top or bottom) should be a ground
layer. Separate analog ground and power ground with a 0Ω
resistor is highly NOT recommended. Directly connect GND
PAD to low noise area of the system ground with at least 4
vias.
2 Never place controller and its external components above or
under VIN plane or any switching nodes.
3 Never share CSRTN and VSEN on the same trace.
4 Place the input rail decoupling ceramic capacitors close to
the high-side FET on the same layer as possible. Never use
only one via and a trace to connect the input rail decoupling
ceramics capacitors; must connect to VIN and GND planes.
5 Place all decoupling capacitors in close proximity to the
controller and the system ground plane.
6 Connect remote sense (VSEN and RGND) to the load and
ceramic decoupling capacitors nodes; never run this pair
below or above switching noise plane.
7 Always double check critical component pinout and their
respective footprints.
Voltage Regulator Design Materials
To support VR design and layout, Intersil also developed a set of
tools and evaluation boards, as listed in Tables 14 and 15,
respectively. Contact Intersil’s local office or field support at
www.intersil.com/ask for the latest available information.
TABLE 14. AVAILABLE DESIGN ASSISTANCE MATERIALS
ITEM
1
DESCRIPTION
SMBus/PMBus/I²C communication tool with
PowerNavigator GUI
2
Evaluation board schematics in OrCAD format and
layout in allegro format. See Table 15 for details.
TABLE 15. AVAILABLE DEMO BOARDS
DEMO BOARD
ISL68200DEMO1Z
ISL68201_99140DEMO1Z
DESCRIPTION
17x17mm² 1-phase, 20A solution,
400kHz, with Dual FET
17x17mm² 1-phase, 35A solution,
400kHz, with ISL99140
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FN8705.1
March 7, 2016