ISL68200 Datasheet, PDF (29/32 Pages) Intersil Corporation – Single-Phase R4 Digital Hybrid PWM Controller with Integrated Driver

ISL68200
0.6
0.4
I_L(P-P) = 0.75 I_O
I_L(P-P) = 0
I_L(P-P) = 0.5 I_O
0.2
00
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_OUT/V_IN)
FIGURE 31. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
Design and Layout Considerations
To ensure a first pass design, the schematics design must be
done right and the board must be carefully laid out.
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board or internal layers.
The ground-plane layer should be in between power layers and
the signal layers to provide shielding, often the layer below the
top and the layer above the bottom should be the ground layers.
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, GND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. Input high frequency capacitors should be
placed close to the drain of the upper MOSFETs and the source of
the lower MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High frequency
output decoupling capacitors (ceramic) should be placed as
close as possible to the decoupling target, making use of the
shortest connection paths to any internal planes. Place the
components in such a way that the area under the IC has less
noise traces with high dV/dt and di/dt, such as gate signals,
phase node signals and VIN plane.
Tables 12 and 13 provide design and layout checklists that
designer must pay attention to.
TABLE 12. DESIGN AND LAYOUT CHECKLIST
PIN
NOISE
NAME SENSITIVITY
DESCRIPTION
EN
Yes There is an internal 1µs filter. Decoupling the
capacitor is NOT needed, but if needed, use a
low time constant one to avoid too large a
shutdown delay.
VIN
Yes Place 16V+ X7R 1µF in close proximity to VIN
pin and the system ground plane.
7VLDO
Yes Place 10V+ X7R 1µF in close proximity to
7VLDO pin and the system ground plane.
VCC
Yes Place X7R 1µF in close proximity to VCC pin
and the system ground plane.
SCL, SDA
Yes
50kHz to 1.25MHz signal when the SMBus,
PMBus, or I²C is sending commands. Pairing
up with SALERT and routing carefully back to
SMBus, PMBus or I²C master. 20 mils spacing
within SDA, SALERT, and SCL; and more than
30 mils to all other signals. Refer to the
SMBus, PMBus or I²C design guidelines and
place proper terminated (pull-up) resistance
for impedance matching. Tie them to GND
when not used.
SALERT
No
Open drain and high dv/dt pin during
transitions. Route it in the middle of SDA and
SCL. Tie it to GND when not used.
PGOOD
No
Open-drain pin. Tie it to ground when not used.
RGND,
VSEN
Yes Differential pair routed to the remote sensing
points with sufficient decoupling ceramics
capacitors and not across or go above/under
any switching nodes (BOOT, PHASE, UGATE,
LGATE) or planes (VIN, PHASE, VOUT) even
though they are not in the same layer. At least
20 mils spacing from other traces. DO NOT
share the same trace with CSRTN.
CSRTN
Yes Connect to the output rail side of the output
inductor or current sensing resistor pin with a
series resistor in close proximity to the pin. The
series resistor sets the current gain and should
be within 40Ωand 3.5kΩ. Decoupling
(~0.1µF/X7R) on the output end (not the pin)
is optional and might be required for long
sense trace and a poor layout (see Figures 9
and 10 on page 16).
CSEN
Yes Connect to the phase node side of the output
inductor or current sensing resistor pin with
L/DCR or ESL/R_SEN matching network in close
proximity to CSEN and CSRTN pins.
Differentially routing back to the controller
with at least 20 mils spacing from other
traces. Should NOT cross or go above/under
the switching nodes [BOOT, PHASE, UGATE,
LGATE] and power planes (VIN, PHASE, VOUT)
even though they are not in the same layer.
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FN8705.1
March 7, 2016