ISL6307 Datasheet, PDF (30/34 Pages) Intersil Corporation – 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current

ISL6307
Case 2:
---------1----------
2π LC
≤
f₀
<
-2---_π----C-----₍-1-E-----S----R-----₎
R_C
=
R_F
B
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 34
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 34 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 21, provides the
necessary compensation.
C₂
R_C ^CC
COMP
FB
C₁
R₁
R_FB
IDROOP
VDIFF
FIGURE 21. COMPENSATION CIRCUIT FOR ISL6307 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f_HF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f_HF = 10f₀, but it can be
higher if desired. Choosing f_HF to be lower than 10f₀ can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 35, R_FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 35.
R₁
=
R_F
B
----------C----⁽---E----S-----R-----⁾---------
LC – C(ESR)
C₁
=
-----L---C------^–-----C-----⁽--E-----S----R-----⁾
R_FB
C₂
=
-----------------------0----.-7----5---V-----^I-^N-------------------------
(2π)²f₀f_HF LCR_FBV_PP
R_C
=
---V-----^P----^P----^--2----^π---^---²----f--⁰---f--^H----^F----L----C----R-----^F----^B----
0.75 V_{IN }2πf_HF LC–1_
C_C
=
--0----.-7----5----V----^I--^N----^-2----^π----f--^H----^F--------L----C-----^–---1---^---
(2π)²f₀f_HF LCR_FBV_PP
(EQ. 35)
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_PP is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V_MAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
30
FN9224.0
March 9, 2006