ISL6307 Datasheet, PDF (21/34 Pages) Intersil Corporation – 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current

ISL6307
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I_AVG, flows from FB through a
load-line regulation resistor, R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V_DROOP = I_AVG R_FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
V_OUT
=
V_REF
–
V_O
F
F
SET
–



I--_{O-----U----T--}
6
-----^R-----^X-------
R_ISEN

R _{F B}
(EQ. 9)
Where V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_OUT is the total output current
of the converter, R_ISEN is the sense resistor in the ISEN line,
N is the number of active channels, and R_FB is the feedback
resistor. R_X has a value of DCR, resistor or R_DS(ON), or
R_SENSE depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to:
R_LL
=
--R----^F----^B--
N
-----^R-----^X-------
R_ISEN
(EQ. 10)
Output-Voltage Offset Programming
The ISL6307 allows the designer to accurately adjust the
offset voltage. When a resistor, R_OFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into OFS. If
R_OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I_OFS flows out of OFS. A resistor
between DAC and REF, R_REF, is selected so that the
product (I_OFS x R_OFS) is equal to the desired offset voltage.
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6307. The current flow through R_REF creates an offset
at the REF pin, which is ultimately duplicated at the output of
the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
1_----._--6_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--4_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 12)
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
VCC
OR
GND
-
1.6V
+
+
0.4V
-
R_OFS
ISL6307CR
OFS
VCC
GND
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6307
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6307 checks the VID inputs six times every switching
cycle. If the VID code is found to have been changed, the
controller waits half of a complete cycle before executing a
12.5mV change. If during the half-cycle wait period, the
difference between DAC level and the new VID code
changes, no change is made. If the VID code is more than
1 bit higher or lower than the DAC (not recommended), the
21
FN9224.0
March 9, 2006