ISL6307 Datasheet, PDF (22/34 Pages) Intersil Corporation – 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current

ISL6307
controller will execute 12.5mV changes six times per cycle
until VID and DAC are equal. It is for this reason that it is
important to carefully control the rate of VID stepping in 1-bit
increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R_REF and C_REF is required for an ISL6307
based voltage regulator. The selection of R_REF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of C_REF is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T_VID, the relationship between the time constant of
R_REF and C_REF network and T_VID is given by Equation 13.
C_REF R_REF = T_VID
(EQ. 13)
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
ISL6307 INTERNAL CIRCUIT EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
10kΩ
EN_PWR
910Ω
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6307 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6307 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
2. The ISL6307 features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6307 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6307 becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6307 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6307 begins the
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6307 reads the VID
code at VID input pins. If the VID code is valid, ISL6307 will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6307 will shut down. Cycling Vcc, EN_PWR
or EN_VTT is needed to restart.
Soft-Start
ISL6307 based VR has 4 periods during soft-start, as shown
in Figure 11. After Vcc, EN_VTT and EN_PWR reach their
POR and enable thresholds, The controller will have fixed
delay period TD1. After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V,
Vboot voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period, TD3. At the end of
TD3 period, ISL6307 will read the VID signals. If the VID
code is valid, ISL6307 will initiate the second soft-start ramp
until the voltage reaches the VID voltage minus offset
voltage.
The soft-start time is the sum of the 4 periods as shown in
the following equation.
T_SS = TD1 + TD2 + TD3 + TD4
(EQ. 14)
TD1 is the fixed delay with typical value as 1.36ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to valid the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6307 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor Rss from SS pin to GND. The 2
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FN9224.0
March 9, 2006