ISL6307 Datasheet, PDF (29/34 Pages) Intersil Corporation – 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current

ISL6307
of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled Channel-Current
Balance). Choose R_ISEN,2 in proportion to the desired
decrease in temperature rise in order to cause proportionally
less current to flow in the hotter phase.
R _{I S E N ,2}
=
R_ISEN
∆_-----T----2-
∆T₁
(EQ. 31)
In Equation 31, make sure that ∆T₂ is the desired temperature
rise above the ambient temperature, and ∆T₁ is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 31 is usually
sufficient, it may occasionally be necessary to adjust R_ISEN
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labelled R_FB in Figure 8.
Its value depends on the desired full-load droop voltage
(V_DROOP in Figure 8). If Equation 30 is used to select each
ISEN resistor, the load-line regulation resistor is as shown in
Equation 32.
R_FB = -V₅----₀^D----^R_×---1-^O---0--^O-_–---_6P--
(EQ. 32)
If one or more of the ISEN resistors are adjusted for thermal
balance, as in Equation 31, the load-line regulation resistor
should be selected according to Equation 33 where I_FL is the
full-load operating current and R_ISEN(n) is the ISEN resistor
connected to the n^th ISEN pin.
∑ ^R_FB
=
----V-----^D----^R----^O-----^O----^P------
I_FL r_DS(ON)
R_ISEN(n)
n
(EQ. 33)
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
C₂ (OPTIONAL)
R_C ^CC
COMP
R_FB
+
V_DROOP
-
FB
IDROOP
VDIFF
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6307 CIRCUIT
The feedback resistor, R_FB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f₀. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there are a separate
set of equations for the compensation components
Case 1:
---------1----------
2π LC
>
f₀
R_C
=
R_F
B
2----π_{----f--0---V-----p---p-------L----C---}
0.75 V _{I N}
C_C = _2----π----0V---.-_P-7---5_P----VR----^I-_F-^N--_B----f--₀--
.
Case 3:
f₀
>
--------------1---------------
2πC(ESR)
R_C = R_{FB 0----.--7--2-5---}^π--V--f--^0I--_N-V----₍-^p-E--^p---SL----R-----₎
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_PP is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 21). Keep
29
FN9224.0
March 9, 2006