X9418_06 Datasheet, PDF (3/20 Pages) Intersil Corporation – Dual Digitally Controlled Potentiometers

PIN CONFIGURATION
V_CC
R_L0/V_L0
R_H0/V_H0
R_W0/V_W0
A2
WP
SDA
A1
R_L1/V_L1
R_H1/V_H1
R_W1/V_W1
V_SS
DIP/SOIC
1
24
2
23
3
22
4
21
5
20
6
7
X9418
19
18
8
17
9
16
10
5
11
14
12
13
V+
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
V-
SDA
A1
R_L1/V_L1
R_H1/V_H1
R_W1/V_W1
V_SS
NC
NC
NC
V-
SCL
A3
TSSOP
1
24
2
23
3
22
4
21
5
20
6
7
X9418
19
18
8
17
9
16
10
15
11
14
12
13
WP
A2
V_W0/R_W0
V_H0/R_H0
V_L0/R_L0
V_CC
NC
NC
NC
V+
A0
NC
PIN NAMES
Symbol
SCL
SDA
A0 - A3
V_H0/R_H0 - V_H1/R_H1,
V_L0/R_L0 - V_L1/R_L1
V_W0/R_W0 -
V_W1/R_W1
WP
V+,V-
V_CC
V_SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
X9418
PRINCIPLES OF OPERATION
The X9418 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9418 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9418 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t_LOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9418 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t_HIGH). The X9418 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
3
FN8194.3
October 12, 2006