ISL75051SEH Datasheet, PDF (3/18 Pages) Intersil Corporation – 3A, Rad Hard, Positive, Ultra Low Dropout Regulator

ISL75051SEH
Pin Configuration
ISL75051SEH
(18 LD CDFP)
TOP VIEW
GND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VADJ
BYP
1
18
2
17
3
16
4
15
5
GND ¹⁴
6
13
7
12
8
11
9
10
PG
VIN
VIN
VIN
VIN
VIN
VIN
OCP
EN
Pin Descriptions
PIN NUMBER
12, 13, 14
15, 16, 17
18
1
2, 3, 4
5, 6, 7
8
9
10
11
Top Lid
PIN NAME
V_IN
PG
GND
V_OUT
VADJ
BYP
EN
OCP
GND
Input supply pins
DESCRIPTION
V_OUT in regulation signal. Logic low defines when V_OUT is not in regulation. Must be grounded if not used.
GND pin
Output voltage pins
VADJ pin allows V_OUT to be programmed with an external resistor divider.
To filter the internal reference, connect a 0.1µF capacitor from BYP pin to GND.
V_IN independent chip enable. TTL and CMOS compatible.
Allows current limit to be programmed with an external resistor.
The top lid is connected to GND pin of the package.
Ordering Information
ORDERING
NUMBER
PART NUMBER
(NOTES 1, 2)
TEMP
RANGE (°C)
PACKAGE
PKG DWG. #
5962R1121202VXC
ISL75051SEHVF
-55 to +125 18 Ld CDFP
K18.D
5962R1121202V9A
ISL75051SEHVX
-55 to +125
ISL75051SRHF/PROTO
ISL75051SRHF/PROTO
-55 to +125 18 Ld CDFP
K18.D
ISL75051SRHEVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL75051SEH. For more information on MSL please see Tech Brief TB363.
3
FN8294.0
August 28, 2012