ISL75051SEH Datasheet, PDF (14/18 Pages) Intersil Corporation – 3A, Rad Hard, Positive, Ultra Low Dropout Regulator

ISL75051SEH
Applications Information
Input Voltage Requirements
This RH LDO will work from a V_IN in the range of 2.2V to 6.0V. The
input supply can have a tolerance of as much as ±10% for
conditions noted in the “Electrical Specifications” table starting
on page 4. Minimum guaranteed input voltage is 2.2V. However,
due to the nature of an LDO, V_IN must be some margin higher
than the output voltage, plus dropout at the maximum rated
current of the application, if active filtering (PSRR) is expected
from V_IN to V_OUT. The dropout spec of this family of LDOs has
been generously specified to allow applications to design for
efficient operation.
Adjustable Output Voltage
The output voltage of the RH LDO can be set to any user
programmable level between 0.8V to 5.0V. This is achieved with
a resistor divider connected between the OUT, ADJ and GND pins.
With the internal reference at 0.52V, the divider ratio should be
fixed such that when the desired VOUT level is reached, the
voltage presented to the ADJ pin is 0.52V. Resistor values for
typical voltages are shown in Table 1.
TABLE 1. RESISTOR VALUES FOR TYPICAL VOLTAGES
V_OUT
0.8V
R_BOTTOM
7.87k
R_TOP
4.32k
1.5V
2.26k
4.32k
1.8V
1.74k
4.32k
2.5V
1.13k
4.32k
4.0V
634
4.32k
5.0V
499
4.32k
Input and Output Capacitor Selection
RH operation requires the use of a combination of tantalum and
ceramic capacitors to achieve a good volume-to-capacitance
ratio. The recommended combination is a 220µF, 25mΩ 10V
DSSC 04051-032 rated tantalum capacitor in parallel with a
0.1µF MIL-PRF-49470 CDR04 ceramic capacitor, to be
connected between V_IN to GND pins and V_OUT to GND pins of the
LDO, with PCB traces no longer than 0.5cm.
The stability of the device depends on the capacitance and ESR
of the output capacitor. The usable ESR range for the device is
6mΩ to 100mΩ. At the lower limit of ESR = 6mΩ, the phase
margin is about 51°C. On the high side, an ESR of 100mΩ is
found to limit the gain margin at around 10dB. The typical
GM/PM seen with capacitors are shown in Table 2.
TABLE 2. TYPICAL GM/PM WITH VARIOUS CAPACITORS
CAPACITANCE
(µF)
ESR
(mΩ)
GAIN MARGIN PHASE MARGIN
(dB)
(°)
47
35
14
55
100
25
16
57
220
6
19
51
220
25
16
69
100
100
10
62
Type numbers of KEMET capacitors used in the device are shown
in Table 3.
TABLE 3. KEMET CAPACITORS USED IN DEVICE
KEMET TYPE NUMBER
CAPACITOR DETAILS
T525D476M016ATE035
47µF, 10V, 35mΩ
T525D107M010ATE025
100µF, 10V, 25mΩ
T530D227M010ATE006
220µF, 10V, 6mΩ
T525D227M010ATE025
220µF, 10V, 25mΩ
T495X107K016ATE100
100µF, 16V, 100mΩ
A typical gain phase plot measured on the ISL75051SRHEVAL1Z
evaluation board for V_IN = 3.3V, V_OUT = 1.8V and I_OUT = 3A with a
220µF, 10V, 25mΩ capacitor is shown in Figure 27 and is
measured at GM = 16.3dB and PM = 69.16°.
60
50
40
30
20
10
0
-10 3.3V
-20 _1.8V
-30 _3.0A
-40 _1x220µF
-50 _T525D
-60
500
5k
PHASE
GAIN
50k
500k
180
150
120
90
60
30
0
-30
-60
-90
-120
-150
-180
5M
FREQUENCY (Hz)
FIGURE 27. TYPICAL GAIN PHASE PLOT
Enable
The device can be enabled by applying a logic high on the EN pin.
The enable threshold is typically 0.9V. A soft-start cycle is
initiated when the device is enabled using this pin. Taking this pin
to logic low disables the device.
EN can be driven from either an open drain or a totem pole logic
drive between EN pin and GND. Assuming an open drain
configuration, M1 will actively pull down the EN line, as shown in
Figure 28, and thereby discharge the input capacitance, shutting
off the device immediately.
14
FN8294.0
August 28, 2012