ISL75051SEH Datasheet, PDF (15/18 Pages) Intersil Corporation – 3A, Rad Hard, Positive, Ultra Low Dropout Regulator

ISL75051SEH
VIN
R1
10k
INT EN GATE
EN PIN
INT EN BUS
M1
EN
0
FIGURE 28. ENABLE
Power-Good
The Power-Good pin is asserted high when the voltage on the ADJ
pin crosses the rising threshold of 0.9 x V_ADJ typ. On the falling
threshold, Power-Good is asserted low when the voltage on the
ADJ pin crosses the falling threshold of 0.88 x V_ADJ. The
power-good output is an open-drain output rated for a continuous
sink current of 1mA.
Soft-start
Soft-start is achieved by means of the charging time constant of
the BYP pin. The capacitor value on the pin determines the time
constant and can be calculated using Equation 1:
T_S = 0.00577xC_S
(EQ. 1)
where T_S = soft-start time in ms, and C_S = BYPASS capacitor in nF.
The BYPASS capacitor, C1, charges with a 90µA source current
and provides an EA reference, -IN, with an SS ramp. V_OUT, in turn,
follows this ramp. The ramp rate can be calculated based on the
C1 value. For conditions in which C1 is opened, or for small
values of C1, the ramp is provided by C2 = 50pF, with a source of
0.5µA. Connecting C1 min = 0.1µF to the BYPASS pin is
recommended for normal operation.
ADJ PIN
VIN
VIN
BYPASS
EXT PIN
I1
90µAdc
I2
0.5µAdc
U1
+IN
INT SS NODE _{-IN OUT}
-IN
VIN
75051_PMOS
M1
C1
0.1µF
C2
50pF
ISL75051SEH EA
VOUT
0
0
FIGURE 29. SOFT-START
Current Limit Protection
The RH LDO incorporates protection against overcurrent due to
any short or overload condition applied to the output pin. The
current limit circuit becomes a constant current source when the
output current exceeds the current limit threshold, which can be
adjusted by means of a resistor connected between the OCP pin
and GND. If the short or overload condition is removed from V_OUT,
then the output returns to normal voltage mode regulation. OCP
can be calculated with Equation 2:
OCP = 9.5 • EXP(–0.6 • (ROCP ⁄ (1 + 0.1ROCP)))
(EQ. 2)
where OCP = Overcurrent Threshold in amps, and ROCP = OCP
resistor in kΩ.
In the event of an overload condition based on the set OCP limit,
the die temperature may exceed the internal over-temperature
limit, and the LDO begins to cycle on and off due to the fault
condition (Figure 30). However, thermal cycling may never occur
if the heatsink used for the package can keep the die
temperature below the limits specified for thermal shutdown.
8
7
6
5
4
3
OCP = +25°C
2
1
0
0
1
2
3
4
5
6
ROCP (kΩ)
FIGURE 30. OCP vs ROCP OVER TEMP
Thermal Guidelines
If the die temperature exceeds typically +175°C, then the LDO
output shuts down to zero until the die temperature cools to
typically +155°C. The level of power combined with the thermal
impedance of the package (θ_JC of 4°C/W for the 18 Ld CDFP
package) determines whether the junction temperature exceeds
the thermal shutdown temperature specified in the “Electrical
Specifications” table.
The device should be mounted on a high effective thermal
conductivity PCB with thermal vias, per JESD51-7 and JESD51-5.
Place a silpad between package base and PCB copper plane. The
VIN and VOUT ratios should be selected to ensure that dissipation
for the selected VIN range keeps T_J within the recommended
operating level of 150°C for normal operation.
Weight Characteristics
Weight of Packaged Device
K18.D: 1.07 Grams typical with leads clipped
15
FN8294.0
August 28, 2012