ISL5239 Datasheet, PDF (3/31 Pages) Intersil Corporation – Pre-Distortion Linearizer

Functional Block Diagram
ISL5239 Pre-Distortion Linearizer
IIN<17:0>
QIN<17:0>
CLKOUT
ISTRB
TMS
TDI
TCK
TRST
TDO
TRIGIN
OFFSET
BINARY
DE-MUX
INPUT TYPE
(PAR/SERIAL)
BYPASS BYPASS BYPASS
HALF
BAND
HALF
BAND
HBAANLFDI _/
/
18
FILTER
1
/
20
/ ^FILTER
2
/
20
/
FILT3ERQ
IFIP I,Q
I
CM TEST _Q
JTAG
TEST
FUNC. SEL.
OFFSET
SCALE
PD MAG.
LUT DATA I
LUT DATA Q
LUT DELTA DATA I
LUT DELTA DATA Q
ACTIVE LUT
LUT ADDR
LUT ADDR AUTO INCR.
LUT
ADDRESS
CALCULATION
ADDR
DATA
LUT
BYPASS
BYPASS
BYPASS
IF
CONV.
CORRECTION
FILTER
REAL 1X
REAL 2X
COMPLEX
GAIN /
PHASE
OFFSET
ADJUST.
OUTPUT
DATA
FORMATTER
8-18 BIT-WIDTH
BYPASS
MODE
HM, KM, LM, GM, DC OFFSETS
OUTPUT WORD WIDTH SEL.
OUTPUT VALUE TYPE
COEF. DATA
REAL PIPELINE SEL.
COEF. ADDR.
MECMHOARNYNELFF3ECT
COMPENSATION
SERIAL INPUT EN.
COEF. B SELECT
PD MAG.
MAX
MIN
THRESHOLD
COMPARE
PWR INTGR PER.
PWR LOW
PWR HIGH
COEF. A
COEF. B
SERIAL TO PAR.
POWER
INTEGRATOR
uP
IFIP I,Q
PD I,Q
PD MAG.
TRIG SEL
TRIG
INPUT DELAY
COUNT
SER. OUTPUT EN.
FB DELAY COUNT
INPUT
SEL
uP
INPUT
STATE
FB
STATE
uP FORMAT
PAR. TO SERIAL
SERIN
SERCLK
SERSYNC
SEROUT
TRIGOUT
CLK
A<5:0>
P<15:0>
CS
WR
RD
BUSY
RESET
DATA ADDR
INPUT
CAPTURE
MEMORY 2K
CM TEST I,Q
MEMORY SELECT
ADDR DATA
FEEDBACK
CAPTURE
MEMORY 1K
uP INTERFACE
IOUT<17:0>
QOUT<17:0>
EXTERNAL
MEMORY
EFFECTS
FPGA
FBCLK
FB<19:0>