ISL5239 Datasheet, PDF (17/31 Pages) Intersil Corporation – Pre-Distortion Linearizer

ISL5239
AC Electrical Specifications V_CCC = 1.8± 5%, V_CCIO = 3.3 ± 5%, T_A = -40^oC to 85^oC (Note 6) (Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
Hold Time SERIN from CLK (Note 7)
t _DHS
1
ns
Delay Time from CLK to TRIGOUT
t _PDC
2 (Note 7)
7
ns
Setup Time from TRIGIN to CLK
t _DS1
2
ns
Hold Time TRIGIN from CLK
t _DH1
2
ns
Setup Time from TMS and TDI to TCK
t _TS
3
ns
Hold Time TMS and TDI from TCK
t _TH
3
ns
Delay Time from TCK to TDO valid
t _TD
8
ns
Test Clock Frequency
f_T
50
MHz
Output Rise/Fall Time (Note 7)
t _RF
-
3
ns
NOTES:
6. AC tests performed with C_L = 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
Test V_IH = 3.0V, V_IHC = 3.0V, V_IL = 0V, V_OL = 1.5V, V_OH = 1.5V.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
8. Can be asynchronous to CLK, specification guarantying which CLK edge the device comes out of reset on.
9. Can be asynchronous to CLK, specification guarantying which CLK edge the device begins the read cycle on.
AC Test Load Circuit
S₁
DUT
C_L †
SWITCH S₁ OPEN FOR I_CCSB AND I_CCOP
† TEST HEAD CAPACITANCE
±
I_OH
1.5V
I_OL
EQUIVALENT CIRCUIT
Waveforms
t_CLK
t_CH t_CL
t_CLK = 1 / F_CLK
CLK
t_RH
t_RS
t_RPW
RESET
FIGURE 15. CLOCK AND RESET TIMING
CLK
t_SC1,t_SCN
SERCLK
SERSYNC
t_SD1
t_SD2
SEROUT
SERIN
t_DSS
t_DHS
FIGURE 16. SERIAL INTERFACE RELATIVE TIMING
17