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ISL6313_14 Datasheet, PDF (27/33 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
ISL6313
desired overcurrent trip level, IOCP, be chosen so that it’s
30% larger then the maximum load current expected.
RSET
=
--------D-----C-----R----------
100 × 10–6
⋅
-I-O-----C----P--
N
⋅
4----0---0--
3
*Note: RSET must be between 20kΩ and 80kΩ
(EQ. 35)
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R1 to match the time constants
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 21. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
2. Record ΔV1 and ΔV2 as shown in Figure 21.
3. Select new values, R1(NEW), for the time constant
resistor based on the original value, R1(OLD), using
Equation 36.
R1(NEW) = R1(OLD) ⋅ ΔΔ----VV----12--
(EQ. 36)
4. Replace R1 with the new value and check to see that the
error is corrected. Repeat the procedure if necessary.
ΔV2
ΔV1
VOUT
ITRAN
ΔI
FIGURE 21. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
If loadline regulation is desired, the resistor on the FS pin,
RT, should be connected to Ground in order for the internal
average sense current to flow out across the loadline
regulation resistor, labeled RFB in Figure 7. This resistor’s
value sets the desired loadline required for the application.
The desired loadline, RLL, can be calculated by Equation 37
where VDROOP is the desired droop voltage at the full load
current IFL.
.
RLL
=
V-----D----R----O-----O----P--
IFL
(EQ. 37)
Based on the desired loadline, the loadline regulation
resistor, RFB, can be calculated from Equation 38.
RFB
=
-R----L---L-----⋅---N------⋅---R----S----E----T-- ⋅ ----3-----
DCR
400
*Note: RFB must be not exceed 4.0kΩ
(EQ. 38)
In Equation 38, RLL is the loadline resistance; N is the
number of active channels; DCR is the DCR of the individual
output inductors; and RSET is the RSET pin resistor.
If no loadline regulation is required, the resistor on the FS
pin, RT, should be connected to the VCC pin. To choose the
value for RFB in this situation, please refer to “Compensation
without load-line regulation” on page 28.
IOUT Pin Resistor
A copy of the average sense current flows out of the IOUT
pin, and a resistor, RIOUT, placed from this pin to ground can
be used to set the overcurrent protection trip level. Based on
the desired overcurrent trip threshold, IOCP, the IOUT pin
resistor, RIOUT, can be calculated from Equation 39.
RIOUT
=
D-----RC----S-R---E---⋅-T--I--O-⋅---NC----P--
⋅
----6-----
400
(EQ. 39)
APA Pin Component Selection
A 100µA current flows into the APA pin and across RAPA to
set the APA trip level. A 1000pF capacitor, CAPA, should
also be placed across the RAPA resistor to help with noise
immunity. Use Equation 40 to set RAPA to get the desired
APA trip level. An APA trip level of 500mV is recommended
for most applications.
RAPA
=
-V----A----P----A---(---T---R----I--P----)
100 × 10–6
=
-----5---0----0----m-----V-------
100 × 10–6
=
5kΩ
(EQ. 40)
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATION WITH LOAD-LINE REGULATION
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, RC and CC.
27
FN6448.2
September 2, 2008