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ISL6313_14 Datasheet, PDF (18/33 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
ISL6313
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 7, a current proportional to the average
current of all active channels, IAVG, flows from FB through a
load-line regulation resistor RFB. The resulting voltage drop
across RFB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as Equation 9:
VDROOP = IAVG ⋅ RFB
(EQ. 9)
For Negative Offset (connect ROFS to VCC):
ROFS
=
--1---.--6-----⋅---R----F----B---
VOFFSET
For Positive Offset (connect ROFS to GND):
ROFS
=
--0---.--3-----⋅---R----F----B---
VOFFSET
VSEN
+
VOFS RFB
-
VREF
E/A
FB
IOFS
(EQ. 12)
(EQ. 13)
The regulated output voltage is reduced by the droop voltage
VDROOP. The output voltage as a function of load current is
derived by combining Equations 6, 8, and 9.
VOUT
=
VREF
–
VO
F
S
–
⎛
⎜
⎝
-I-O-----U----T--
N
⋅
---D----C-----R-----
RISEN
⋅
⎞
R F B⎠⎟
(EQ. 10)
In Equation 10, VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total output current
of the converter, RISEN is the internal sense resistor
connected to the ISEN+ pin, RFB is the feedback resistor, N
is the active channel number, and DCR is the Inductor DCR
value.
Therefore the equivalent loadline impedance, i.e. droop
impedance, is equal to:
RLL
=
--R----F----B-- ⋅
N
---D----C-----R-----
RISEN
(EQ. 11)
Output-Voltage Offset Programming
The ISL6313 allows the designer to accurately adjust the
offset voltage by connecting a resistor, ROFS, from the OFS
pin to VCC or GND. When ROFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (IOFS) to flow into the OFS pin
and out of the FB pin, providing a negative offset. If ROFS is
connected to ground, the voltage across it is regulated to
0.3V, and IOFS flows into the FB pin and out of the OFS pin,
providing a positive offset. The offset current flowing through
the resistor between VSEN and FB will generate the desired
offset voltage which is equal to the product (IOFS x RFB).
These functions are shown in Figures 8 and 9.
Once the desired output offset voltage has been determined,
use Equations 12 and 13 to set ROFS:
18
ROFS
OFS
ISL6313
GND
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VSEN
-
VOFS RFB
+
VREF
E/A
FB
IOFS
VCC
ROFS
OFS
ISL6313
+
0.3V
-
-
1.6V
+
GND
VCC
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
FN6448.2
September 2, 2008