ISL6313_14 Datasheet, PDF (21/33 Pages) Intersil Corporation – Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6313
from shutdown mode to begin the soft-start startup
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6313 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6313 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6313 in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pin must
reach the internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the ISL6313 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 6).
For Intel VR11 and AMD 6-bit modes of operation these are
the only conditions that must be met for the controller to
immediately begin the soft-start sequence. If running in AMD
5-bit mode of operation there is one more condition that
must be met:
4. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different then the AMD soft-start
sequence.
For the Intel VR11 mode of operation, the soft-start
sequence if composed of four periods, as shown in
Figure 13. Once the ISL6313 is released from shutdown and
soft-start begins (as described in “Enable and Disable” on
page 20), the controller will have a fixed delay period TD1 of
typically 1.10ms. After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V
VBOOT voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed delay period t_d3, of typically
93µs. At the end of t_d3 period, ISL6313 will read the VID
signals. It is recommended that the VID codes be set no
later then 50µs into period t_d3. If the VID code is valid,
ISL6313 will initiate the second soft-start ramp until the
output voltage reaches the VID voltage plus/minus any offset
or droop voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 19.
t_SS = t_d1 + t_d2 + t_d3 + t_d4
(EQ. 19)
V_OUT, 500mV/DIV
t_d1
t_d2
EN
t_d3 t_d4 t_d5
PGOOD
500µs/DIV
FIGURE 13. SOFT-START WAVEFORMS
During t_d2 and t_d4, ISL6313 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS on the SS pin. The second
soft-start ramp time t_d2 and t_d4 can be calculated based on
Equations 20 and 21:
t_d2 = 1.1 ⋅ R_SS ⋅ 8 ⋅ 10^–3(μs)
(EQ. 20)
t_d4 = V_VID – 1.1 ⋅ R_SS ⋅ 8 ⋅ 10^–3(μs)
(EQ. 21)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_d2 will be 880µs and the
second soft-start ramp time t_d4 will be 320µs.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t_d5. The typical value
for t_d5 is 93µs.
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of two periods, as shown in
Figure 14. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t_dA of typically 1.10ms. After this delay period
the ISL6313 will begin ramping the output voltage to the
desired DAC level at a fixed rate of 6.25mV per step. The
time for each step is determined by the frequency of the
soft-start oscillator which is defined by the resistor R_SS on
the SS pin. The amount of time required to ramp the output
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FN6448.2
September 2, 2008