82C237 Datasheet, PDF (23/25 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

Timing Waveforms (Continued)
82C237
S0
S11
S12
S13
S14
S21
S22
S23
S24
S11/SI
CLK
(33)
TCLSH
ADSTB
TFAAB (22)
TASS (11)
A0-A7
(34)
TCLSL
TFADB (24)
(33)
TCLSH
(7)
TAHS
(59) TRHSH
ADDRESS VALID
(5) TAFDB _TASS
(11)
(34)
TCLSL
TAHS
(7)
TWHSH
(60)
ADDRESS VALID
TAFDB
(5)
DB0-DB7
TFAC (23)
MEMR
TFAC (23)
A8-A15
TDCL
(15)
IN
(16) TDCTR
TAZRL _TIDS
(64)
(27)
A8-A15
(24)
TFADB _TOVD
TIDH (26) ⁽²⁹⁾
TDCTW (17)
TDCL
(15)
TDCL
(15)
OUT
MEMW
DWLE
(SEE NOTE)
TASS (11)
TAHS
(7)
EXTENDED WRITE
TASS (11) _TAK(9)
TAHS
(7)
TOEV (65)
TCLSH
(33)
TAFAB
(3)
TODH (28)
TAFAC
(4)
TAFAC
(4)
TAK
(9)
EOP
EXT EOP
(19) TEPH
TEPS (20)
TEPW
(21)
FIGURE 13. MEMORY-TO-MEMORY TRANSFER
NOTE: For 16-bit mode, 82C237 only. In 8-bit mode this signal is always high impedance three-stated. Waveform shown is for a 16-bit memory-to-memory
transfer. For an 8-bit transfer in 16-bit mode, DWLE will go high at least TASS before the falling edge of ADSTB in S2, then low TAHS after the falling
edge of ADSTB, and will remain low until the next ADSTB where the cycle is repeated.
CLK
READ
WRITE
READY
S2
S3
SW
(15)
TDCL
(15)
TDCL
(15)TDCL
EXTENDED WRITE
(31)TRH
(32)TRS
(31)
TRH
SW
(32) TRS
S4
(16)
TDCTR
(17)
TDCTW
FIGURE 14. READY
NOTE: READY must not transition during the specified setup and hold times.
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