82C237 Datasheet, PDF (19/25 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

82C237
AC Electrical Specifications
V_CC
=
+5.0V
±10%,
GND
=
0V,
TTT_AAA===0--^o_45C05ootoCC
+70^oC (C82C237),
to +85^oC (I82C237),
to +125^oC (M82C237)
82C237
82C237-12
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
DMA (MASTER) MODE
(1)TAEL
AEN HIGH from CLK LOW (S1) Delay Time
-
105
-
50
(2)TAET
AEN LOW from CLK HIGH (SI) Delay Time
-
80
-
50
(3)TAFAB
ADR Active to Float Delay from CLK HIGH
-
55
-
55
(4)TAFC
READ or WRITE Float Delay from CLK HIGH
-
75
-
50
(5)TAFDB
DB Active to Float Delay from CLK HIGH
-
135
-
90
(6)TAHR
ADR from READ HIGH Hold Time
TCY-75
-
TCY-65
-
(7)TAHS
DB from ADSTB LOW Hold Time
TCL-18
-
TCL-18
-
(8)TAHW
ADR from WRITE HIGH Hold Time
TCY-65
-
TCY-50
-
(9)TAK
DACK Valid from CLK LOW Delay Time
-
105
-
69
EOP HIGH from CLK HIGH Delay Time
-
105
-
90
EOP LOW from CLK HIGH Delay Time
-
60
-
35
(10)TASM
ADR Stable from CLK HIGH
-
60
-
50
(11)TASS
DB to ADSTB LOW Setup Time
TCH-20
-
TCH-20
-
(12)TCH
CLK HIGH Time (Transitions 10ns)
55
-
30
-
(13)TCL
CLK LOW Time (Transitions 10ns)
43
-
30
-
(14)TCY
CLK Cycle Time
125
-
80
-
(15)TDCL
CLK HIGH to READ or WRITE LOW Delay
-
130
-
120
(16)TDCTR
READ HIGH from CLK HIGH (S4) Delay Time
-
115
-
80
(17)TDCTW
WRITE HIGH from CLK HIGH (S4) Delay Time
-
80
-
70
(18)TDQ
HRQ Valid from CLK HIGH Delay Time
-
75
-
30
(19)TEPH
EOP Hold Time from CLK LOW (S2)
90
-
50
-
(20)TEPS
EOP LOW to CLK LOW Setup Time
25
-
0
-
(21)TEPW
EOP Pulse Width
135
-
50
-
(22)TFAAB
ADR Valid Delay from CLK HIGH
-
60
-
50
(23)TFAC
READ or WRITE Active from CLK HIGH
-
90
-
50
(24)TFADB
DB Valid Delay from CLK HIGH
-
60
-
45
(25)THS
HLDA Valid to CLK HIGH Setup Time
45
-
10
-
(26)TIDH
Input Data from MEMR HIGH Hold Time
0
-
0
-
(27)TIDS
Input Data to MEMR HIGH Setup Time
90
-
45
-
(28)TODH
Output Data from MEMW HIGH Hold Time
15
-
TCY-50
-
(29)TODV
Output Data Valid to MEMW HIGH
TCY-35
-
TCY-10
-
(30)TQS
DREQ to CLK LOW (SI, S4) Setup Time
0
-
0
-
(31)TRH
CLK to READY LOW Hold Time
20
-
10
-
(32)TRS
READY to CLK LOW Setup Time
35
-
15
-
(33)TCLSH
ADSTB HIGH from CLK LOW Delay Time
-
70
-
70
(34)TCLSL
ADSTB LOW from CLK LOW Delay Time
-
120
-
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4-166