82C237 Datasheet, PDF (22/25 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

82C237
Timing Waveforms (Continued)
CLK
DREQ
SI
SI
TQS
(30)
TDQ
(18)
S0
S0
S1 S2 S3
S4 S2 S3 S4 SI
SI
SI
TQS
(30)
TCY
(14)
TCL (13)
TDQ
(18)
TCH
(12)
HRQ
DWLE
(SEE NOTE)
HLDA
AEN
ADSTB
DB0-DB7
A0-A7
DACK
READ
WRITE
INT EOP
EXT EOP
THS
(25)
TASS
(11)
TAHS
(7)
TAEL
(1)
TCLSH
(33)
TFADB
(24)
A8-A15
TFAAB
(22)
TAK
(9)
TFAC
(23)
TDVAL (61)
TDCL (15)
TAET
(2)
TCLSL
(34)
TSHSL
(37)
TASS
(11)
TAHS
(7)
TAFDB
(5)
ADDRESS VALID
(64)
TAZRL
TDCL
(15)
TDCTR
(16)
TWRRD
(35)
TDCTW
(17)
TEPS
(20)
TEPH
(19)
TRHAL
(58)
TAK (9)
TASM
(10)
TAHW
(8)
ADDRESS VALID
TAHR
(6)
TAFAB (3)
TAHW (8)
TAHR (6)
TRHDI (63)
TAVRL
(56)
TDCL
(15)
TRLRH
(36)
TAVWL
(57)
TAFC (4)
TDCTR (16)
TDCTW (17)
TWLWH (39)
(FOR EXTENDED WRITE)
TDVWL TWLWHA
(62)
(38)
(FOR EXTENDED WRITE)
TDCL
(15)
TAK (9)
TAK (9)
TEPW (21)
FIGURE 12. DMA TRANSFER
NOTE: For 16-bit mode, 82C237 only. In 8-bit mode this signal is always high impedance three-stated. Waveform shown is for an 8-bit transfer
with the 82C237 programmed in 16-bit mode. For a 16-bit transfer, DWLE will go low at least TASS before the falling edge of ADSTB in S2,
and remain low for the entire transfer.
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