82C237 Datasheet, PDF (17/25 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

82C237
Figure 9 shows the data bus for a 16-bit DMA application
with the 82C237. High memory and low memory are
selected accordingly with A0 and the 8/16 signal during DMA
transfers. The 8/16 signal is formed from DWLE with a D flip-
flop and ADSTB. ADSTB must be inverted to the D flip-flop
since DWLE is set up to the falling edge of ADSTB and the
74F74 latches data on the rising edge of CLK.
The ADSTB inverted could be eliminated by using a 74F75
falling edge D latch. The latch on D8-D15 is needed for 16-
bit memory-to-memory transfers. The upper eight bits of
data are latched by MEMR during the read half of the trans-
fer. The data is then enabled onto the data bus during the
write half of the transfer.
80C286
D8-D15
D0-D7
82C237
D0-D7
IOR
IOW
MEMR
MEMW
DWLE
A0 ADSTB
V_CC
LATCH
(SEE NOTE)
OE
STB
TRANSCEIVER
TRANSCEIVER
D8-D15
D0 - D7
74F74
D Q ^8/16
CLK
HIGH
MEMORY
CS
LOW
MEMORY
CS
I/O
DEVICE
I/O
DEVICE
HLDA
MEMCS
FROM DECODER
NOTE: Only needed for memory-to-memory transfers.
FIGURE 9. DATA BUS FOR 16-BIT DMA APPLICATION
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