82C237 Datasheet, PDF (12/25 Pages) Intersil Corporation – CMOS High Performance Programmable DMA Controller

82C237
If an active channel is cascaded, as defined by its mode reg-
ister, DWLE will be driven low at the start of the transfer, and
will remain low for the entire transfer. This allows the DWLE
signal from the slave 82C237 to control the system. To form
the system DWLE signal for cascaded 82C237s, simply “OR”
the individual DWLE outputs of the Master and Slaves.
or 16-bit transfers. Data bits 4-7 represent DREQ channels 0-
3 respectively and determine the data width (8-bit or 16-bit) of
each channel during DMA transfers. When programming this
register, bit 3 of the data must be set to “0”. Since the address
of the Data-Width register is the same as the Mask register,
bit 3 selects which register is actually written.
Registers Affected by 16-Bit
Transfer Mode
Data-Width Register - 16-bit transfer mode enabled
76543210
BIT NUMBER
Current Address Register - Each channel has a 16-bit Cur-
rent Address register. This register holds the value of the
address used during DMA transfers. On channels pro-
grammed to perform 8-bit DMA transfers, the address is
automatically incremented or decremented by one after
each transfer. On channels programmed for 16-bit DMA
transfers, the address is automatically incremented or decre-
mented by two after each transfer.
During all 16-bit transfers, the A0 output will remain low for
the entire transfer, even if an odd address is programmed
into the channel’s Current Address register (i.e. only even
word addresses will be generated).
The Current Address register is written or read by the micro-
processor in successive 8-bit bytes. See Figure 6 for pro-
gramming information. It may also be reinitialized by an
Autoinitialize back to its original value. Autoinitialize takes
place only after an EOP. In memory-to-memory mode, the
channel 0 Current Address register can be prevented from
incrementing or decrementing by setting the address hold bit
in the Command register.
Current Word Count Register - Each channel has a 16-bit
Current Word Count register. This register determines the
number of transfers to be performed. On channels pro-
grammed for 8-bit transfers, the actual number of transfers
will be one more than the number programmed in the Cur-
rent Word Count register (i.e. programming a count of 100
will result in 101 transfers). The word count is decremented
by one after each transfer on 8-bit transfer channels.
On channels programmed for 16-bit transfers, the word
count is decremented by two after each transfer. This means
that for even values in the Current Word Count register, the
actual number of transfers will be n/2 + 1, where n is the
value in the Current Word Count register. For odd values in
this register, the actual number of transfers will be (n+1)/2.
When the value in the Current Word Count register decre-
ments past zero (i.e. 0 to FFFEH or 1 to FFFFH), a TC will
be generated.
This register is loaded or read in successive 8-bit bytes by
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC on 8-bit transfers, or
FFFEH after TC on 16-bit transfers.
Data-Width Register - When 16-bit transfer mode is enabled,
the Data-Width register becomes accessible and is used to
program each DMA channel to perform either 8-bit transfers
X Don’t Care
0 Must be 0 to write all
data - width bits
0 Channel 0 = 16-bit transfers
1 Channel 0 = 8-bit transfers
0 Channel 1 = 16-bit transfers
1 Channel 1 = 8-bit transfers
0 Channel 2 = 16-bit transfers
1 Channel 2 = 8-bit transfers
0 Channel 3 = 16-bit transfers
1 Channel 3 = 8-bit transfers
Mask Register - In 16-bit transfer mode this register oper-
ates the same as the previous Mask register description with
the exception of bit 3 when writing the instruction to sepa-
rately set or clear a mask bit. Bit 3 of the data must be “1”
when writing a single mask bit. Bits 4-7 are ignored when
this instruction is written. Refer to the following diagram for
writing single mask bits.
Mask Register - 16-bit transfer mode enabled
76543210
BIT NUMBER
Don’t Care
00 Select channel 0 mask bit
01 Select channel 1 mask bit
10 Select channel 2 mask bit
11 Select channel 3 mask bit
0 Clear mask bit
1 Set mask bit
1 Must be 1 to write single
mask bit
The software command to write all four bits of the Mask reg-
ister has no effect on the state of the Data-Width bits.
When reading the Mask/Data-Width register (they share the
same address), bits 0-3 will always display the mask bits of
channels 0-3, respectively. With 16-bit transfer mode not
enabled, bits 4-7 will always read as logical ones. With 16-bit
transfer mode enabled, bits 4-7 will display the data-width
bits for channels 0-3 respectively.
The Mask and Data-Width registers are set by RESET or
Master Clear. This disables all hardware DMA requests until
a clear mask bit instruction allows them to be recognized.
RESET or Master Clear forces the Mask and Data-Width
4-159