ISL6252 Datasheet, PDF (22/25 Pages) Intersil Corporation – Highly Integrated Battery Charger Controller for Notebook Computers

ISL6252, ISL6252A
TABLE 3.
CELLS
2
R₃
288kΩ
R₄
48kΩ
3
320kΩ
64kΩ
4
336kΩ
96kΩ
Choose R_VCOMP equal or lower than the value calculated
from Equation 43:
VCOMP
=
( 0.7
⋅
f_LC
)
⋅
(
2
π
⋅
C_o
⋅
R_SENSE)
⋅
⎛
⎝
g^----m^-5-----1^{--⎠⎞}
⋅
⎛
⎜
⎝
-^R----³--_R---+--₄--^R-----⁴-_{⎠⎟⎞}
(EQ. 43)
Next, choose C_VCOMP equal or higher than the value
calculated from Equation 44:
C_VCOMP
=
-----------------------------------¹-------------------------------------
(0.3 ⋅ f_LC) ⋅ (2π ⋅ R_VCOMP)
(EQ. 44)
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown in the following:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will
shield other noise couplings through the IC, should be used
as signal ground beneath the IC. The best tie-point between
the signal ground and the power ground is at the negative
side of the output capacitor on each side, where there is little
noise; a noisy trace beneath the IC is not recommended.
GND and VDD Pin
At least one high quality ceramic decoupling capacitor
should be used to cross these two pins. The decoupling
capacitor can be put close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the
buck converter. The signal going through this trace has both
high dv/dt and high di/dt, and the peak charging and
discharging current is very high. These two traces should be
short, wide, and away from other traces. There should be no
other traces in parallel with these traces on any layer.
PGND Pin
PGND pin should be laid out to the negative side of the
relevant output capacitor with separate traces.The negative
side of the output capacitor must be close to the source node
of the bottom MOSFET. This trace is the return path of
LGATE.
PHASE Pin
This trace should be short, and positioned away from other
weak signal traces. This node has a very high dv/dt with a
voltage swing from the input voltage to ground. No trace
should be in parallel with it. This trace is also the return path
for UGATE. Connect this pin to the high-side MOSFET
source.
UGATE Pin
This pin has a square shape waveform with high dv/dt. It
provides the gate drive current to charge and discharge the
top MOSFET with high di/dt. This trace should be wide,
short, and away from other traces similar to the LGATE.
BOOT Pin
This pin’s di/dt is as high as the UGATE; therefore, this trace
should be as short as possible.
CSOP, CSON, CSIP and CSIN Pins
Accurate charge current and adapter current sensing is
critical for good performance. The current sense resistor
connects to the CSON and the CSOP pins through a low
pass filter with the filter capacitor very near the IC (see
Figure 2). Traces from the sense resistor should start at the
pads of the sense resistor and should be routed close
together, throughout the low pass filter and to the CSON and
CSON pins (see Figure 25). The CSON pin is also used as
the battery voltage feedback. The traces should be routed
away from the high dv/dt and di/dt pins like PHASE, BOOT
pins. In general, the current sense resistor should be close
to the IC. These guidelines should also be followed for the
adapter current sense resistor and CSIP and CSIN. Other
layout arrangements should be adjusted accordingly.
22
FN6498.3
August 25, 2010