ISL6252 Datasheet, PDF (17/25 Pages) Intersil Corporation – Highly Integrated Battery Charger Controller for Notebook Computers

ISL6252, ISL6252A
The LGATE gate driver can drive sufficient gate current to
switch most MOSFETs efficiently. However, some FETs may
exhibit cross conduction (or shoot through) due to current
injected into the drain-to-source parasitic capacitor (C_gd) by
the high dV/dt rising edge at the phase node when the
high-side MOSFET turns on. Although LGATE sink current
(1.8A typical) is more than enough to switch the FET off
quickly, voltage drops across parasitic impedances between
LGATE and the MOSFET can allow the gate to rise during
the fast rising edge of voltage on the drain. MOSFETs with
low threshold voltage (<1.5V) and low ratio of C_gs/C_gd (<5)
and high gate resistance (>4Ω) may be turned on for a few
ns by the high dV/dt (rising edge) on their drain. This can be
avoided with higher threshold voltage and C_gs/C_gd ratio.
Another way to avoid cross conduction is slowing the turn-on
speed of the high-side MOSFET by connecting a resistor
between the BOOT pin and the boot strap capacitor.
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage as shown in
Equation 22:
P_{Q1, conduction}
=
V_{-----O----U----T--}
V_IN
⋅
I_B
A
2
T
⋅
r_D
S
(ON)
(EQ. 22)
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include the MOSFET internal gate resistance, gate charge,
threshold voltage, stray inductance, pull-up and pull-down
resistance of the gate driver.
The following switching loss calculation (Equation 23)
provides a rough estimate.
Q1, Switching ⁼
(EQ. 23)
V_I
N
I_L
V
f_s
w
⎛
⎜
⎝
I^--_g^---_,^---Q_s^---_o^-g--_u^--d--_r^--_c^---_e^-_{⎠⎟⎞}
+
1_--
2
V_I
N
I_LP
⎛
f _{s w ⎝⎜}
I^--_g^--Q-_,^---_s^-g--_i^-dn----_k^-_{⎠⎟⎞}
+
Q_rrV_INf_sw
where the following are the peak gate-drive source/sink
current of Q₁, respectively:
• Q_gd: drain-to-gate charge
• Q_rr: total reverse recovery charge of the body-diode in
low-side MOSFET
• I_LV: inductor valley current
• I_LP: Inductor peak current
• I_g,sink
• I_g,_source
Low switching loss requires low drain-to-gate charge Q_gd.
Generally, the lower the drain-to-gate charge, the higher the
ON-resistance. Therefore, there is a trade-off between the
ON-resistance and drain-to-gate charge. Good MOSFET
selection is based on the Figure of Merit (FOM), which is a
product of the total gate charge and ON-resistance. Usually,
the smaller the value of FOM, the higher the efficiency for
the same application.
For the low-side MOSFET, the worst-case power dissipation
occurs at minimum battery voltage and maximum input
voltage (Equation 24):
P_Q2
=
⎛
⎜1
⎝
–
V_{----V-O---I-U-N---T--⎠⎟⎞}
⋅
I_B
2
AT
⋅
r_D
S
(
O
N
)
(EQ. 24)
Choose a low-side MOSFET that has the lowest possible
ON-resistance with a moderate-sized package (like the
SO-8) and is reasonably priced. The switching losses are
not an issue for the low-side MOSFET because it operates
at zero-voltage-switching.
Choose a Schottky diode in parallel with low-side MOSFET
Q₂ with a forward voltage drop low enough to prevent the
low-side MOSFET Q₂ body-diode from turning on during the
dead time. This also reduces the power loss in the high-side
MOSFET associated with the reverse recovery of the
low-side MOSFET Q₂ body diode.
As a general rule, select a diode with DC current rating equal
to one-third of the load current. One option is to choose a
combined MOSFET with the Schottky diode in a single
package. The integrated packages may work better in
practice because there is less stray inductance due to a
short connection. This Schottky diode is optional and may be
removed if efficiency loss can be tolerated. In addition,
ensure that the required total gate drive current for the
selected MOSFETs is less than 24mA. So, the total gate
charge for the high-side and low-side MOSFETs is limited by
Equation 25:
Q_GAT
E
≤
1_{----G-----A---T----E--}
f_sw
(EQ. 25)
Where I_GATE is the total gate drive current and should be
less than 24mA. Substituting I_GATE = 24mA and f_s = 300kHz
into Equation 25 yields that the total gate charge should be
less than 80nC. Therefore, the ISL6252 easily drives the
battery charge current up to 10A.
Snubber Design
ISL6252's buck regulator operates in discontinuous current
mode (DCM) when the load current is less than half the
peak-to-peak current in the inductor. After the low-side FET
turns off, the phase voltage rings due to the high impedance
with both FETs off. This can be seen in Figure 9. Adding a
snubber (resistor in series with a capacitor) from the phase
node to ground can greatly reduce the ringing. In some
situations a snubber can improve output ripple and
regulation.
The snubber capacitor should be approximately twice the
parasitic capacitance on the phase node. This can be
17
FN6498.3
August 25, 2010