ISL6252 Datasheet, PDF (19/25 Pages) Intersil Corporation – Highly Integrated Battery Charger Controller for Notebook Computers

ISL6252, ISL6252A
RAMP GEN
V_RAMP = VDD/11
-
+
PWM
INPUT
VDD
L
CO
PWM
GAIN = 11
L
11
R _{FET_rDS(ON)}
PWM
INPUT
R _SENSE
R _{L_DCR}
CO
R_ESR
R _BAT
FIGURE 18. SMALL SIGNAL AC MODEL
In most cases the Battery resistance is very small (<200mΩ)
resulting in a very low Q in the output filter. This results in a
frequency response from the input of the PWM to the
inductor current with a single pole at the frequency
calculated in Equation 29:
f_POLE1
=
(_---R_{----S----E----N-----S---E-----+-----}r_{---D----S----(--O----N----)----+-----}R_{----D----C-----R-----+-----}R_{----B----A----T----})
2π ⋅ L
(EQ. 29)
The output capacitor creates a pole at a very high frequency
due to the small resistance in parallel with it. The frequency
of this pole is calculated in Equation 30:
f_POLE2
=
------------------¹--------------------
2π ⋅ C_o ⋅ R_BAT
(EQ. 30)
CHARGE CURRENT CONTROL LOOP
When the battery voltage is less than the fully charged
voltage, the voltage error amplifier goes to it’s maximum
output (limited to 1.2V above ICOMP) and the ICOMP
voltage controls the loop through the minimum voltage
buffer. Figure 19 shows the charge current control loop.
PHASE
L
11
R_FET_r_DS(ON)
R_{L_DCR}
The compensation capacitor (C_ICOMP) gives the error
amplifier (GMI) a pole at a very low frequency (<<1Hz) and a
a zero at f_Z1. f_Z1 is created by the 0.25*CA2 output added to
ICOMP. The frequency of can be calculated from
Equation 31:
f_ZERO = ₍---₂----_π---⁴--_â‹---_C^â‹---^g-_I--_C-^m---_O--²---_M----_P-----₎
gm2
=
5_----0_----μ_----A_--
V
(EQ. 31)
Placing this zero at a frequency equal to the pole calculated
in Equation 29 will result in maximum gain at low frequencies
and phase margin near 90°. If the zero is at a higher
frequency (smaller C_ICOMP), the DC gain will be higher but
the phase margin will be lower. Use a capacitor on ICOMP
that is equal to or greater than the value calculated in
Equation 32:
C_ICOMP = ₍---_R-----_S---₂-----+-----_r--_D----_S-⁴---₍--^â‹_O---⁽--_N⁵----⁰₎---+^μ----^A-_R-----_D^⁄--^V--_C---⁾-_R-----+-----_R-----_B----_A---_T----₎
(EQ. 32)
A filter should be added between R_S2 and CSOP and CSON
to reduce switching noise. The filter roll off frequency should
be between the crossover frequency and the switching
frequency (~100kHz). R_F2 should be small (<10Ω) to
minimize offsets due to leakage current into CSOP. The filter
cut-off frequency is calculated using Equation 33:
f_FILTER = ₍---₂----_π-----_â‹---_C----_F-¹---₂----_â‹---_R-----_F---₂----₎
(EQ. 33)
The crossover frequency is determined by the DC gain of the
modulator and output filter and the pole in Equation 29. The
DC gain is calculated in Equation 34 and the crossover
frequency is calculated with Equation 35.
A_DC
=
------------------------------------------¹----¹-----^â‹---^R----^S----²-------------------------------------------
(R_S2 + r_DS(ON) + R_DCR + R_BATTERY)
(EQ. 34)
f_CO
=
A_DC ⋅ f_POLE1
=
1_----1_-----⋅_---R_----S----2-
2π ⋅ L
(EQ. 35)
+
S^Σ
0.25
-
ICOMP
C_ICOMP
-
gm2
+
+
20
-
CA2
CSOP
CSON
CHLIM
+
-
R _F2
C_F2
R_S2
C_O
R_ESR
R_BAT
FIGURE 19. CHARGE CURRENT LIMIT LOOP
19
FN6498.3
August 25, 2010