ISL6307A Datasheet, PDF (21/33 Pages) Intersil Corporation – Ultra-high bandwidth 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current Sensing

ISL6307A
and another voltage rail. The enable comparator holds
the ISL6307A in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6307A becomes enabled. The schematic in Figure 10
illustrates the sequencing of the ISL6307A with the
ISL66xx family of Intersil MOSFET drivers, which require
12V bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6307A begins
the soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for a fixed delay time, ISL6307A reads the
VID code at the VID input pins. If the VID code is valid,
ISL6307A will regulate the output to the final VID setting. If
the VID code is an OFF code, ISL6307A will shut down.
Cycling Vcc, EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6307A based VR has four periods during soft-start, as
shown in Figure 11. After Vcc, EN_VTT and EN_PWR reach
their POR and enable thresholds, there’s a fixed delay
period TD1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V, Vboot
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period, TD3. At the end of TD3 period,
ISL6307A will read the VID signals. If the VID code is valid,
ISL6307A will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the four periods as shown in
the following equation.
T_SS = TD1 + TD2 + TD3 + TD4
(EQ. 14)
TD1 is the fixed delay with typical value as 1.36ms. TD3 is
determined by the fixed 85µs time plus the time to obtain
valid VID voltage. If the VID is valid before the output
reaches the 1.1V, the minimum time to check the VID input is
500ns. Therefore, the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6307A digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor Rss from SS pin to GND. The two
soft-start ramp times, TD2 and TD4, can be calculated
based on the following equations.
TD2
=
1_----._-1_----x_----R_{----S----S-- (µs)}
6.25 x 25
(EQ. 15)
TD4
=
(_{---V----V----I--D-----}–_-----1_---._--1_----)_--x_---R_{-----S----S--}
6.25 x 25
(µs)
(EQ. 16)
For example, when VID is set to 1.5V and Rss is set at
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
VOUT, 500mV/DIV
VR_RDY, 5V/DIV
TD1
TD2 TD3 TD4 TD5
EN_VTT, 1V/DIV
500µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6307A actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 12
outlines the interaction between the fault monitors and the
power good signal, VR_RDY.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful soft-
start and a delay time, TD5. TD5 is typically 85µs. VR_RDY
will be pulled low when an undervoltage or overvoltage
condition is detected, or the controller is disabled by a reset
from EN_PWR, EN_VTT, POR, or a VID OFF-code.
21
FN9236.0
February 6, 2006