ISL6307A Datasheet, PDF (20/33 Pages) Intersil Corporation – Ultra-high bandwidth 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current Sensing

ISL6307A
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
VCC
OR
GND
-
1.6V
+
+
0.4V
-
R_OFS
OFS
ISL6307ACR
VCC
GND
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6307A
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6307A checks the VID inputs six times every
switching cycle. If the VID code is found to have been
changed, the controller waits half of a complete cycle before
executing a 12.5mV change. If during the half-cycle wait
period, the difference between DAC level and the new VID
code changes, no change is made. If the VID code is more
than 1 bit higher or lower than the DAC (not recommended),
the controller will execute 12.5mV changes six times per
cycle until VID and DAC are equal. It is for this reason that it
is important to carefully control the rate of VID stepping in 1-
bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R_REF and C_REF is required for an ISL6307A
based voltage regulator (see Figure 8). The selection of
R_REF is based on the desired offset as detailed above in
Output-Voltage Offset Programming section. The selection
of C_REF is based on the time duration for 1 bit VID change
and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T_VID, the relationship between the time constant of
R_REF and C_REF network and T_VID is given by Equation 13.
C_REF R_REF = T_VID
(EQ. 13)
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
ISL6307A INTERNAL CIRCUIT EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
10kΩ
EN_PWR
910Ω
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6307A
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6307A will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications).
2. The ISL6307A features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
20
FN9236.0
February 6, 2006