ISL6307A Datasheet, PDF (19/33 Pages) Intersil Corporation – Ultra-high bandwidth 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current Sensing

ISL6307A
TABLE 1. VID CODE (Continued)
VID7 VID6 VID5 ^{VID4 VID3} VID2 VID1 VID0 ^DAC
800mV 400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV VOLTAGE
1
0
0
1
1
1
0
0 0.63750
1
0
0
1
1
1
0
1 0.63125
1
0
0
1
1
1
1
0 0.62500
1
0
0
1
1
1
1
1 0.61875
1
0
1
0
0
0
0
0 0.61250
1
0
1
0
0
0
0
1 0.60625
1
0
1
0
0
0
1
0 0.60000
1
0
1
0
0
0
1
1 0.59375
1
0
1
0
0
1
0
0 0.58750
1
0
1
0
0
1
0
1 0.58125
1
0
1
0
0
1
1
0 0.57500
1
0
1
0
0
1
1
1 0.56875
1
0
1
0
1
0
0
0 0.56250
1
0
1
0
1
0
0
1 0.55625
1
0
1
0
1
0
1
0 0.55000
1
0
1
0
1
0
1
1 0.54375
1
0
1
0
1
1
0
0 0.53750
1
0
1
0
1
1
0
1 0.53125
1
0
1
0
1
1
1
0 0.52500
1
0
1
0
1
1
1
1 0.51875
1
0
1
1
0
0
0
0 0.51250
1
0
1
1
0
0
0
1 0.50625
1
0
1
1
0
0
1
0 0.50000
1
1
1
1
1
1
1
0 OFF
1
1
1
1
1
1
1
1 OFF
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I_AVG, flows from FB through a
load-line regulation resistor, R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V_DROOP = I_AVG R_FB
(EQ. 8)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage, as a function of load current, is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
V_OUT
=
V_REF
–
V_O
F
F
SET
–



-I-^O-----^U----^T--
N
------^R----^X-------
R_ISEN

R _{F B}
(EQ. 9)
V_REF is the reference voltage and V_OFS is the programmed
offset voltage. I_OUT is the total output current of the
converter, R_ISEN is the sense resistor in the ISEN line, N is
the number of active channels, and R_FB is the feedback
resistor. R_X has a value of DCR, resistor or R_DS(ON), or
R_SENSE, depending on the sensing method.
Therefore, the equivalent load-line impedance, i.e. Droop
impedance, is equal to:
R_LL
=
--R----^F----^B--
N
-----^R-----^X-------
R_ISEN
(EQ. 10)
Output-Voltage Offset Programming
The ISL6307A allows the designer to accurately adjust the
offset voltage. When a resistor, R_OFS, is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I_OFS) to flow into OFS. If
R_OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I_OFS flows out of OFS. A resistor
between DAC and REF, R_REF, is selected so that the
product (I_OFS x R_OFS) is equal to the desired offset voltage.
These functions are shown in Figure 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
1_----._--6_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--4_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 12)
19
FN9236.0
February 6, 2006