ISL6307A Datasheet, PDF (16/33 Pages) Intersil Corporation – Ultra-high bandwidth 6-Phase PWM Controller with 8 Bit VID Code Capable of Precision RDS(ON) or DCR Differential Current Sensing

ISL6307A
+
V_COMP
-
+
PWM1
-
FILTER f(jω) ^{SAWTOOTH SIGNAL}
I₆
I_ER
I_AVG
÷N
-
+
I₅
Σ
I₄
I₃
I₂
I₁
FIGURE 7. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The integrating compensation network shown in Figure 8
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6307A to include the
combined tolerances of each of these elements.
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry which control
voltage regulation is illustrated in Figure 8.
EXTERNAL CIRCUIT
R_C C_{C COMP}
R_REF
C_REF
DAC
REF
FB
R_FB
+
IDROOP
V_DROOP
-
VDIFF
ISL6307A INTERNAL CIRCUIT
I_AVG
+
-
V_COMP
ERROR AMPLIFIER
V_OUT+
VSEN
+
V_OUT-
RGND
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The ISL6307A incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point,
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the non-
inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V_DIFF, is
connected to the inverting input of the error amplifier, FB,
through an external resistor, R_FB.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 1. Each VID
input offers a 45µA pull-up to an internal 2.5V source for use
with open-drain outputs. The pull-up current diminishes to
zero above the logic threshold to protect voltage-sensitive
output devices. External pull-up resistors can augment the
pull-up current sources if case leakage into the driving
device is greater than 45µA.
Load-Line Regulation
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load-line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
16
FN9236.0
February 6, 2006