ISL78220 Datasheet, PDF (20/22 Pages) Intersil Corporation – 6-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

ISL78220
Internal 5V LDO Output Current
Limit Derating Curves
ISL78220 contains an internal 5V/200mA LDO, and the input of
LDO (VIN pin) can go as high as 40V. Based on the junction to
ambient thermal resistance R_JA of the package, we need to
guarantee that the maximum junction temperature should be
below +125°C T_MAX. Figure 22 shows the relationship between
maximum allowed LDO output current and input voltage. The
curve is based on +35°C/W thermal resistance R_JA for the
package, different curve represents different ambient
temperature T_A.
Configurations for 12-Phase
Operation
For high power applications, two ISL78220 ICs can be easily
configured to support 12-phase operation. The IC that provide the
CLK_OUT signal is called master IC, and the IC that received the
CLK_OUT signal is called slave IC. Note that the two PWM1
signals are synchronized and the net effect is 6-phase operation
with double the output current.
SYSTEM
DRIVE_EN
DRIVE_EN
CLK_OUT
MASTER IC
DRIVE_EN
SYNC
SLAVE IC
COMP FB SS
COMP FB SS
FIGURE 22. I_LDO(MAX) vs V_IN
Dedicated VREF2 Pin for Input
Voltage Tracking
A second reference input pin, VREF2, is added to the input of the
transconductance amplifier. The ISL78220 internal reference will
automatically change to VREF2 when it is pulled below 1.8V. The
VREF2 pin can be connected to VIN through resistor network to
implement the automatic input voltage tracking function. This
function is very useful under car battery voltage cranking
conditions (such as when the car is parked and the driver is
listening to the stereo), where the full load power is typically not
needed. In this case, the ISL78220 can limit the output power by
allowing the output voltage to track the input voltage. If VREF2 is
not used, the pin should be connected to VCC.
FIGURE 23. CONFIGURATIONS FOR 12-PHASE OPERATION
Figure 23 shows the step-by-step setup as follows:
1. Connect the CLK_OUT pin of the master IC to the SYNC pin of
the slave IC.
2. Set the master IC’s switching frequency as desired frequency,
set the slave IC’s switching frequency 20% below the master
IC’s.
3. Connect both IC’s COMP, SS and FB pins together.
4. Both IC’s DRIVE_EN pin should be AND together to provide
system’s driver enable signal.
5. Since PGOOD, VOUT_OVB and VIN_OVB pins are open drain
structure, both IC’s PGOOD, VOUT_OVB and VIN_OVB pins can
be tied together and use one pull-up resistor to connect to
VCC.
6. If phase dropping function is needed, tie both IC’s IOUT and
MODE pins together.
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FN7688.0
December 15, 2011