ISL78220 Datasheet, PDF (13/22 Pages) Intersil Corporation – 6-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

ISL78220
the PWM outputs can also generate 2.5V tri-level signal. The
external driver can identify this tri-level signal and turn off both
low side and high side output signals accordingly.
The truth table regarding V_MODE and V_{PWM_TRI} for different
mode of applications is summarized in Table 1.
TABLE 1. OPERATION MODE FOR DIFFERENT APPLICATIONS
CASE
MODE
EXTERNAL
DRIVER
IDENTIFY
PWM 2.5V TRI-LEVEL
_TRI SIGNAL?
APPLICATIONS
A
1
1
Yes
Synchronous boost for audio
amplifier power supply. No
phase dropping.
B Analog 1
Yes
Applications that need
improving light load efficiency
(automatic phase dropping +
cycle-by-cycle diode emulation
+ pulse skipping).
C
1
0
No
Applications that the external
driver cannot identify tri-level
signal, no phase dropping.
D Analog 0
No
Applications that the external
driver cannot identify tri-level
signal, with improved light load
efficiency (e.g., 6-phase
non-synchronous boost with
phase dropping).
Considerations for Audio
Amplifier Power Supply
Application
For multiphase boost converters used in audio amplifier
applications, it is preferred to have the following features:
1. Automatic phase dropping function is NOT needed because
the load is fast changing.
2. In car audio amplifier applications, the switching frequency is
preferred to be fixed, such that it will not interfere with
FM/AM band.
3. For synchronous boost, diode emulation is needed during
start-up in order to prevent negative current dumping to the
input side.
4. For synchronous boost, a maximum duty cycle limitation on
the synchronous FET is preferred.
Based on the above mentioned “preferred features”, For audio
amplifier applications, it does not need phase dropping/adding,
but it needs a tri-state PWM signal if synchronous boost structure
is used. Also in order to limit the maximum duty cycle of the
synchronous FET, the minimal turn on time of the active FET
(Low-side FET for boost structure) will be changed from fixed
130ns to variable time, which is 1/12 of the switching periods.
Operation Initialization Before
Soft-Start
Prior to converter initialization, proper conditions must exist on the
enable inputs (EN pin) and VCC pin. When both conditions are met,
the controller begins soft-start. Once the output voltage is within
the proper window of operation, V_PGOOD is asserted logic high.
Figure 14 shows the ISL78220 internal circuit functions before
the soft-start begins.
CIRCUIT INITIALIZATION BEFORE SOFT- START
EN
0
0
t1 t2 t3
t4
t
VCC
POR
t
t5
THEN SOFT- START BEGINS
PWM_DETECTION
t
0
PWM
t
0
FIGURE 14. CIRCUIT INITIALIZATION BEFORE SOFT-START
As shown on Figure 14, there are 5 time intervals before the
soft-start is initialized, they are specified as t₁, t₂, t₃, t₄ and t₅,
respectively. The descriptions for each time interval are as
follows:
Time t₁: The enable comparator holds the ISL78220 in shutdown
until the V_EN rises above 1.2V at the beginning of t₁ time period.
During t₁, V_VCC will gradually increase until it reaches the internal
power-on reset (POR) rising threshold. Then the system enters t₂.
Time t₂: During t₂ time, the device initialization occurs. The time
duration for t₂ is typically from 60µs to 100µs.
Time t₃: The internal PWM detection signal will be asserted and
the system enters the t₃ period. During t₃ the ISL78220 will
detect the voltage on each PWM pin to determine the active
phase number. If PWM1 or PWM2 is accidentally pulled to VCC,
the chip will be latched off and wait for power recycling. The time
duration for t₃ is fixed to around 30µs.
Time t₄: When internal PWM detection signal is released the
system enters t₄ period. During t₄ period the ISL78220 will wait
until the internal PLL circuits are locked to the pre-set oscillator
frequency. When PLL locking is achieved, the oscillator will
generate output at CLK_OUT pin. The time duration for t₄ is
typically around 0.5ms, depending on PLL_COMP pin
configuration.
Time t₅: After the PLL locks the frequency, the system enters the
t₅ period. During t₅ the PWM outputs are held in a
high-impedance state (If V_{PWM_TRI} = 1) or logic low (if
V_{PWM_TRI} = 0), and the V_{DRIVE_EN} is logic LOW to assure the
external drivers remain off. The ISL78220 has one unique
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FN7688.0
December 15, 2011