ISL78220 Datasheet, PDF (2/22 Pages) Intersil Corporation – 6-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

Pin Configuration
ISL78220
ISL78220
(44 LD 10x10 EP-TQFP)
TOP VIEW
FS
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLK_OUT
PWM_INV
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
VIN
ISEN6P
ISEN6N
ISEN4P
ISEN4N
ISEN2P
ISEN2N
ISEN5P
ISEN5N
ISEN3P
ISEN3N
Functional Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
FS
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLKOUT
PWM_INV
DESCRIPTION
A resistor placed from FS to ground will set the PWM switching frequency.
Use this pin to set-up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start
ramp rate and in turn determine the soft-start time.
The output of the transconductance amplifier. Place the compensation network between COMP and GND for
compensation loop design.
The inverting input of the transconductance amplifier. A resistor network should be placed between FB pin and
output rail to set the output voltage.
External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the
internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a
resistor divider network from VCC or VIN.
Bias and reference ground for the IC.
This pin programs the slope of the internal slope compensation. A resistor should be connected from SLOPE pin
to GND. Please refer to “Adjustable Slope Compensation” on page 18 for how to choose the resistor value.
This pin serves as the compensation node for the PLL. A second order passive loop filter connected between
PLL_COMP pin and GND compensates the PLL feedback loop.
Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to
80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input
waveform. If SYNC function is not used, tie SYNC pin to GND. A 500nA current source is connected internally to
pull down the SYNC pin if it is left open.
This pin provides a clock signal to synchronize with another ISL78220. This provides scalability and flexibility. The
rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal.
This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation.
Pulling this pin to VCC will invert the PWM signal. This function provides the flexibility for the ISL78220 to work
with different drivers.
2
FN7688.0
December 15, 2011