ISL6556B Datasheet, PDF (20/24 Pages) Intersil Corporation – Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application

ISL6556B
.
Case 2:
Case 3:
---------1----------
2π LC
≤
f₀
<
--------------1---------------
2πC(ESR)
R_C
=
R_FB
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
f₀
>
--------------1---------------
2πC(ESR)
R_C
=
R_FB
--------2----^π----f--⁰---V-----^p---^p---L---------
0.75 V_IN (ESR)
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
(EQ. 22)
In Equations 22, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V_PP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 4 and Electrical Specifications.
Once selected, the compensation values in Equations 22
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equations 22 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 12). Keep
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ∆I;
the load-current slew rate, di/dt; and the maximum allowable
output-voltage deviation under transient loading, ∆V_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
∆V ≈ (ESL) -d---i + (ESR) ∆I
dt
(EQ. 23)
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the high-
frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I_C,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V_PP(MAX), determines the lower limit on the inductance.
L
≥
(ESR)


V_IN
–
N
V_O
U

T_
V_OUT
-----------------------------------------------------------
f_S V_{I N} V_{P P( M A X )}
(EQ. 24)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆V_MAX. This places an upper limit on inductance.
Equation 25 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 26
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L ≤ ^{2----N-----C-----V---O}----
(∆I)²
∆V_MAX – ∆I(ESR)
(EQ. 25)
L ≤ ⁽---1---.--2---5----⁾--N-----C---
(∆I)²
∆V_MAX – ∆I(ESR)


V_IN
–
V_{O}
(EQ. 26)
20
FN9097.4
December 28, 2004