ISL6556B Datasheet, PDF (16/24 Pages) Intersil Corporation – Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application

ISL6556B
driver ICs reach their POR level before the ISL6556B
becomes enabled. The schematic in Figure 8
demonstrates sequencing the ISL6556B with the
HIP660X family of Intersil MOSFET drivers, which require
12V bias.
3. (ISL6556BCR only) The voltage on ENLL must be logic
high to enable the controller. This pin is typically
connected to the VID_PGOOD. The ISL6556BBCR has
this signal internally connected high.
4. The VID code must not be 111111 or 111110. These
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either
of these codes and will execute soft-start upon receiving
any other code. These codes can be used to enable or
disable the controller but it is not recommended. After
receiving one of these codes, the controller executes a
2-cycle delay before changing the overvoltage trip level to
the shut-down level and disabling PWM. Overvoltage
shutdown cannot be reset using one of these codes.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.24V; For
ISL6556BCR, ENLL must be logic high; and VID cannot be
equal to 111111 or 111110. When each of these conditions
is true, the controller immediately begins the soft-start
sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed VID level. The PWM signals remain in
the high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a pre-
existing charge on the output as the controller attempted to
regulate to zero volts at the beginning of the soft-start cycle.
The soft-start time, t_SS, begins with a delay period equal to
64 switching cycles followed by a linear ramp with a rate
determined by the switching period, 1/f_SW.
t_SS
=
6_----4_-----+_-----1_---2_---8_----0_----⋅_---V_-----I_--D_---
f_SW
(EQ. 11)
For example, a regulator with 250kHz switching frequency
having VID set to 1.35V has t_SS equal to 6.912ms.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft-start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft-start sees the DAC ramping
with 12.5mV steps.
VOUT, 500mV/DIV
2ms/DIV
EN, 5V/DIV
500µs/DIV
FIGURE 9. SOFT-START WAVEFORMS WITH AN UN-BIASED
OUTPUT. FSW = 500kHz
Fault Monitoring and Protection
The ISL6556B actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 10
outlines the interaction between the fault monitors and the
power good signal.
PGOOD
UV
75%
-
OC
+
100µA
I₁
REPEAT FOR
EACH CHANNEL
DAC
REFERENCE
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
100µA
I_AVG
VDIFF
+
OV
-
OVP
VID + 0.2V
FIGURE 10. POWER GOOD AND PROTECTION CIRCUITRY
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD only transitions
low when an undervoltage condition is detected or the
controller is disabled by a reset from EN, ENLL, POR, or one
of the no-CPU VID codes. After an undervoltage event,
16
FN9097.4
December 28, 2004