ISL6556B Datasheet, PDF (18/24 Pages) Intersil Corporation – Optimized Multi-Phase PWM Controller with 6-Bit DAC and Programmable Internal Temperature Compensation for VR10.X Application

ISL6556B
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
current range. If through-hole MOSFETs and inductors can
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 30A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs, inductors
and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r_DS(ON)). In Equation 12, I_M is the maximum
continuous output current; I_PP is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (V_OUT/V_IN); and
L is the per-channel inductance.
P_{LOW, 1}
=
r_DS(ON)



I--_{M---}
N
2
(
1
–
d
)
+
-I-^L---^,---^2P----^P----⁽--1-----^–-----d----⁾
12
(EQ. 12)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON); the switching frequency,
f_S; and the length of dead times, t_d1 and t_d2, at the
beginning and the end of the lower-MOSFET conduction
interval respectively.
P_{LOW, 2}
=
V_D(ON) f_S


I--_M---
N
+
I--_{P-2---P--}
t_d1
+


-I-^M---
N
–
I--_{P----P--}
2
t_d2
(EQ. 13)
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P_LOW,1 and
P_LOW,2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V_IN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Q_rr; and the upper MOSFET r_DS(ON)
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 14,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP,1.
P _{U P,1}
≈
V_IN


-I-^M---
N
+
I--_{P-2---P--}



t--_1--


2_
f_S
(EQ. 14)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 15, the
approximate power loss is P_UP,2.
P_{UP, 2}
≈
V_IN


-I-^M---
^N
–
I--_{P----P--}
2



t--_2--
2



f_S
(EQ. 15)
A third component involves the lower MOSFET’s reverse-
recovery charge, Q_rr. Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q_rr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P_UP,3 and is approximately
P_UP,3 = V_IN Q_rr f_S
(EQ. 16)
Finally, the resistive part of the upper MOSFET’s is given in
Equation 17 as P_UP,4.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 14, 15, 16 and 17. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
P_UP,4 ≈ r_DS(ON)


-I-^M---
 N
2
d
+
-I-^P----^P--²-
12
(EQ. 17)
18
FN9097.4
December 28, 2004