ISL6363 Datasheet, PDF (20/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
VR_HOT#/ALERT# Behavior
Temp Zone
Bit 7 =1
Bit 6 =1
Bit 5 =1
VR Temperature
7
3% Hysteresis
1111 1111
1
10
0111 1111
0011 1111
12 _{0001 1111}
Temp Zone
Register
0001 1111 0011 1111
Status 1
Register = “001”
SVID
2
8
0111 1111
3
= “011”
GerReg ⁵
Status1
1111 1111
0111 1111
0011 1111 0001 1111
= “001”
13 _GerReg 15
Status1
ALERT#
4
6
14
16
VR_HOT#
9
11
FIGURE 14. VR_HOT#/ALERT# BEHAVIOR
The controller drives 60µA current source out of the NTC pin and
the NTCG pin alternatively at 1kHz frequency with 50% duty
cycle. The current source flows through the respective NTC
resistor networks on the pins and creates voltages that are
monitored by the controller through an A/D converter (ADC) to
generate the TZONE value. Table 4 shows the programming table
for TZONE. The user needs to scale the NTC and the NTCG
network resistance such that it generates the NTC (and NTCG) pin
voltage that corresponds to the left-most column. Do not use any
capacitor to filter the voltage.
TABLE 4. TZONE TABLE
VNTC (V)
TMAX (%)
TZONE
0.84
>100
FFh
0.88
100
FFh
0.92
97
7Fh
0.96
94
3Fh
1.00
91
1Fh
1.04
88
0Fh
1.08
85
07h
1.12
82
03h
1.16
79
01h
1.2
76
01h
>1.2
<76
00h
Figure 14 shows how the NTC and the NTCG network should be
designed to get correct VR_HOT#/ALERT# behavior when the
system temperature rises and falls, manifested as the NTC and the
NTCG pin voltage falls and rises. The series of events are:
1. The temperature rises so the NTC pin (or the NTCG pin)
voltage drops. TZONE value changes accordingly.
2. The temperature crosses the threshold where the TZONE
register Bit 6 changes from 0 to 1.
3. The controller changes Status_1 register bit 1 from 0 to 1.
4. The controller asserts ALERT#.
5. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register bit 6 flipping.
6. The controller clears ALERT#.
7. The temperature continues rising.
8. The temperature crosses the threshold where the TZONE
register Bit 7 changes from 0 to 1.
9. The controller asserts the VR_HOT# signal. The CPU throttles
back and the system temperature starts dropping eventually.
10. The temperature crosses the threshold where the TZONE
register bit 6 changes from 1 to 0. This threshold is 1 ADC step
lower than the one when VR_HOT# gets asserted, to provide
3% hysteresis.
11. The controllers de-assert the VR_HOT# signal.
12. The temperature crosses the threshold where the TZONE
register bit 5 changes from 1 to 0. This threshold is 1 ADC step
lower than the one when ALERT# gets asserted during the
temperature rise to provide 3% hysteresis.
13. The controller changes Status_1 register bit 1 from 1 to 0.
14. The controller asserts ALERT#.
15. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register bit 5 flipping.
16. The controller clears ALERT#.
Protection Functions
VR1 and VR2 both provide overcurrent, current-balance and
overvoltage fault protections. The controller also provides
over-temperature protection. The following discussion is based on
VR1 and also applies to VR2.
The controller determines overcurrent protection (OCP) by
comparing the average value of the droop current I_droop with an
internal current source threshold as Table 2 shows. It declares
OCP when I_droop is above the threshold for 120µs.
For overcurrent conditions above 1.5x the OCP level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection. This protection is also referred to as
way-overcurrent protection or fast-overcurrent protection, for
short-circuit protections.
The controller monitors the ISEN pin voltages to determine
current-balance protection. If the ISEN pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
latch off.
The controller takes the same actions for all of the above fault
protections: de-assertion of PGOOD and turn-off of the high-side
and low-side power MOSFETs. Any residual inductor current will
decay through the MOSFET body diodes.
The controller will declare an overvoltage fault and de-assert PGOOD
if the output voltage exceeds the VID set value by +200mV. The
ISL6363 will immediately declare an OV fault, de-assert PGOOD,
and turn on the low-side power MOSFETs. The low-side power
MOSFETs remain on until the output voltage is pulled down below
the VID set value when all power MOSFETs are turned off. If the
output voltage rises above the VID set value +200mV again, the
protection process is repeated. This behavior provides the
maximum amount of protection against shorted high-side power
MOSFETs while preventing output ringing below ground.
20
FN6898.0
September 29, 2011