ISL6363 Datasheet, PDF (11/32 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12™ Desktop CPUs

ISL6363
Gate Driver Timing Diagram
PWM
UGATE
t_LGFUGR
t_RU
t_FU
1V
LGATE
1V
t_FL
t_RL
t_UGFLGR
Theory of Operation
Multiphase R3 Modulator
The ISL6363 is a multiphase regulator implementing Intel’s™
VR12™ protocol. It has two voltage regulators, VR1 and VR2, on
one chip. VR1 can be programmed for 1, 2, 3, or 4-phase
operation, and VR2 is dedicated for 1-phase operation. The
following description is based on VR1, but also applies to VR2
because the same architecture is implemented.
The ISL6363 uses Intersil’s patented R3 (Robust Ripple Regulator)
modulator. The R3 modulator combines the best features of fixed
frequency PWM and hysteretic PWM while eliminating many of
their shortcomings. Figure 3 conceptually shows the multiphase
R3 modulator circuit, and Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C_rm with a current source equal to
g_mV_o, where g_m is a gain factor. C_rm voltage V_crm is a sawtooth
waveform traversing between the VW and COMP voltages. It resets
to VW when it hits COMP, and generates a one-shot master clock
signal. A phase sequencer distributes the master clock signal to
the slave circuits. If VR1 is in 4-phase mode, the master clock
signal will be distributed to the four phases, and the Clock1~4
signals will be 90° out-of-phase. If VR1 is in 3-phase mode, the
master clock signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If VR1 is in 2-phase
mode, the master clock signal will be distributed to Phases 1 and 2,
and the Clock1 and Clock2 signals will be 180° out-of-phase. If
VR1 is in 1-phase mode, the master clock signal will be distributed
to Phase 1 only and be the Clock1 signal.
VW
MASTER CLOCK CIRCUIT
MASTER
MASTER ^COMP
CLOCK _Vcrm
CLOCK
Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CIRCUIT 1
Clock1 S PWM1 ^{Phase1 L1}
Q
R
IL1
gm
SLAVE CIRCUIT 2
Clock2 S PWM2 ^{Phase2 L2}
Q
R
IL2
gm
SLAVE CIRCUIT 3
Clock3 S PWM3 ^{Phase3 L3}
Q
R
IL3
gm
Vo
Co
FIGURE 3. R3 MODULATOR CIRCUIT
Each slave circuit has its own ripple capacitor C_rs, whose voltage
mimics the inductor ripple current. A g_m amplifier converts the
inductor voltage into a current source to charge and discharge
C_rs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C_rs. When C_rs
voltage V_Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C_rs.
11
FN6898.0
September 29, 2011