ISL23445 Datasheet, PDF (2/20 Pages) Intersil Corporation – Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

Block Diagram
VLOGIC
SDI
SDO
SCK
CS
I/O
BLOCK
LEVEL
SHIFTER
Pin Configurations
ISL23445
(20 LD TSSOP)
TOP VIEW
RL0 1
RW0 2
V_CC 3
RH0 4
RL1 5
RW1 6
RH1 7
GND 8
V_LOGIC 9
SDI 10
20 RL3
19 RW3
18 RH3
17 RL2
16 RW2
15 RH2
14 SCK
13 SDO
12 GND
11 CS
ISL23445
(20 LD QFN)
TOP VIEW
20 19 18 17
V_CC 1
RH0 2
RL1 3
RW1 4
RH1 ⁵
GND 6
166 RH3
15 RL2
14 RW2
13 RH2
12 SCK
11 SDO
7 8 9 10
ISL23445
VCC
POWER UP
INTERFACE
CONTROL
AND
STATUS
LOGIC
GND
WR0
VOLATILE
REGISTER
WR1
VOLATILE
REGISTER
WR2
VOLATILE
REGISTER
WR3
VOLATILE
REGISTER
RH0
RW0
RL0
RH1
RW1
RL1
RH2
RW2
RL2
RH3
RW3
RL3
Pin Descriptions
TSSOP QFN
1
19
2
20
3
1
4
5
6
7
8, 12
9
2
3
4
5
6, 10
7
10
8
11
9
13
11
14
12
15
13
16
14
17
15
18
16
19
17
20
18
SYMBOL
DESCRIPTION
RL0 DCP0 “low” terminal
RW0 DCP0 wiper terminal
V_CC Analog power supply.
Range 1.7V to 5.5V
RH0 DCP0 “high” terminal
RL1 DCP1 “low” terminal
RW1 DCP1 wiper terminal
RH1 DCP1 “high” terminal
GND Ground pin
V_LOGIC SPI bus /logic supply
Range 1.2V to 5.5V
SDI Logic Pin - Serial bus data input
CS Logic Pin - Active low chip select
SDO Logic Pin - Serial bus data output
(configurable)
SCK Logic Pin - Serial bus clock input
RH2 DCP2 “high” terminal
RW2 DCP2 wiper terminal
RL2 DCP2 “low” terminal
RH3 DCP3 “high” terminal
RW3 DCP3 wiper terminal
RL3 DCP3 “low” terminal
2
FN7874.0
June 21, 2011