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ISL23445 Datasheet, PDF (16/20 Pages) Intersil Corporation – Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
ISL23445
CS
SCK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SDI
SDO
WR INSTRUCTION
ADDR
DATA BYTE
FIGURE 27. TWO BYTE WRITE SEQUENCE
CS
SCK
SDI
SDO
1
8
RD
ADDR
16
24
32
NOP
RD
ADDR
READ DATA
FIGURE 28. FOUR BYTE READ SEQUENCE
Applications Information
Communicating with ISL23445
Communication with ISL23445 proceeds using SPI interface
through the ACR (address 10000b), WR0 (addresses 00000b),
WR1 (addresses 00001b), WR2 (addresses 00010b), WR3
(addresses 00011b) registers.
The wiper of the potentiometer is controlled by the WRi register.
Writes and reads can be made directly to these registers to
control and monitor the wiper position.
Daisy Chain Configuration
When an application needs more than one ISL23445, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs, as shown in Figure 29. In Daisy Chain
configuration, the SDO pin of the previous chip is connected to
the SDI pin of the following chip, and each CS and SCK pins are
connected to the corresponding microcontroller pins in parallel,
like regular SPI interface implementation. The Daisy Chain
configuration can also be used for simultaneous setting of
multiple DCPs. Note, the number of daisy chained DCPs is
limited only by the driving capabilities of SCK and CS pins of
microcontroller; for larger number of SPI devices, buffering of
SCK and CS lines is required.
Daisy Chain Write Operation
The write operation starts by a HIGH-to-LOW transition on the CS
line, followed by N number of two bytes write instructions on the
SDI line with reversed chain access sequence: the instruction
byte + data byte for the last DCP in chain is going first, as shown
in Figure 30, where N is a number of DCPs in chain. The serial
data is going through DCPs from DCP0 to DCP(N-1) as follows:
DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is
executed on the rising edge of CS for all N DCPs simultaneously.
Daisy Chain Read Operation
The read operation consists of two parts: first, send the read
instructions (N two bytes operation) with valid address; second,
read the requested data while sending NOP instructions (N two
bytes operation), as shown in Figures 31 and 32.
The first part starts by a HIGH-to-LOW transition on the CS line,
followed by N two bytes read instruction on the SDI line with
reversed chain access sequence: the instruction byte + dummy
data byte for the last DCP in chain is going first, followed by a
LOW-to-HIGH transition on the CS line. The read instructions are
executed during the second part of the read sequence. It also
starts by a HIGH-to-LOW transition on the CS line, followed by N
number of two bytes NOP instructions on the SDI line and
LOW-to-HIGH transition of CS. The data is read on every even byte
during the second part of the read sequence while every odd byte
contains code 111b followed by the address from which the data
is being read.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
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FN7874.0
June 21, 2011