ISL23445 Datasheet, PDF (17/20 Pages) Intersil Corporation – Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23445
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients,
but that will also reduce the useful bandwidth of the circuit, thus,
this may not be a good solution for some applications. It may be
a good idea, in this case, to use fast amplifiers in a signal chain
for fast recovery.
V_LOGIC Requirements
It is recommended to keep V_LOGIC powered all the time during
normal operation. In a case where turning V_LOGIC OFF is
necessary, it is recommended to ground the V_LOGIC pin of the
ISL23445. Grounding the V_LOGIC pin or both V_LOGIC and V_CC does
not affect other devices on the same bus. It is good practice to put
a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to
the V_LOGIC pin.
V_CC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V_CC pin.
N DCP IN A CHAIN
CS
SCK
MOSI
MISO
µC
DCP0
CS
SCK
SDI
SDO
DCP1
CS
SCK
SDI
SDO
DCP2
CS
SCK
SDI
SDO
DCP(N-1)
CS
SCK
SDI
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
CS
SCK
SDI
SDO 0
SDO 1
SDO 2
16 CLKLS
WR D C P2
16 CLKS
WR D C P1
WR D C P2
16 CLKS
WR D C P0
WR D C P1
WR D C P2
FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
12
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
SDI
SDO
INSTRUCTION
ADDR
DATA IN
DATA OUT
FIGURE 31. TWO BYTE READ INSTRUCTION
17
FN7874.0
June 21, 2011