ISL23445 Datasheet, PDF (14/20 Pages) Intersil Corporation – Quad, 256 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23445
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the data
bits are shifted out on the falling edge of the serial clock SCK and
will be available to the master on the following rising edge of SCK.
The output type is configured through ACR[1] bit for Push-Pull or
Open Drain operation. The default setting for this pin is Push-Pull.
An external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z) depending on the selected configuration.
CHIP SELECT (CS)
CS LOW enables the ISL23445, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23445 is deselected and the SDO pin is at high impedance,
and the device will be in the standby state.
V_LOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I²C logic source.
Principles of Operation
The ISL23445 is an integrated circuit incorporating four DCPs
with its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
Voltage at any of the DCP pins, RHi, RLi or RWi, should not
exceed V_CC level at any conditions during power-up and normal
operation.
The V_LOGIC pin is the terminal for the logic control digital power
source. It should use the same supply as the SPI logic source,
which allows reliable communication with a wide range of
microcontrollers and is independent from the V_CC level. This is
extremely important in systems where the master supply has
lower levels than the DCP analog supply.
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WR of
a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RWi)
is closest to its “Low” terminal (RLi). When the WRi register of a DCP
contains all ones (WRi[7:0] = FFh), its wiper terminal (RWi) is closest
to its “High” terminal (RHi). As the value of the WRi increases from
all zeroes (0) to all ones (255 decimal), the wiper moves
monotonically from the position closest to RLi to the position closest
to RHi. At the same time, the resistance between RWi and RLi
increases monotonically, while the resistance between RHi and RWi
decreases monotonically.
While the ISL23445 is being powered up, both WRi are reset to
80h (128 decimal), which positions RWi at the center between
RLi and RHi.
The WRi can be read or written to directly using the SPI serial
interface as described in the following sections.
Memory Description
The ISL23445 contains five volatile 8-bit registers: Wiper Register
WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register
WR3 and Access Control Register (ACR). The memory map of
ISL23445 is shown in Table 1. The Wiper Register WRi at address i,
contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access
Control Register (ACR) at address 10h contains information and
control bits described in Table 2.
ADDRESS
(hex)
10
3
2
1
0
TABLE 1. MEMORY MAP
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
ACR
40
WR3
80
WR2
80
WR1
80
WR0
80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME/ 0 SHDN 0 0
0
0 SDO 0
VALUE
The SDO bit (ACR[1]) configures the type of SDO output pin. The
default value of SDO bit is 0 for Push-Pull output. The SDO pin
can be configured as Open Drain output for some applications. In
this case, an external pull-up resistor is required. Reference the
“Serial Interface Specification” on page 7.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e. each DCP is
forced to end-to-end open circuit and each RW shorted to RL
through a 2kΩ serial resistor, as shown in Figure 25. The default
value of the SHDN bit is 1.
RH
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
14
FN7874.0
June 21, 2011