ISL6420A Datasheet, PDF (19/21 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6420A
greater than the maximum input voltage and a voltage
rating of 1.5 x is a conservative guideline. The RMS
current rating requirement for the input capacitor of a
buck regulator is approximately 1/2 the DC load current.
Equation 14 shows a more specific formula for
determining the input ripple:
I_RMS = I_MAX ⋅ (D – D²)
(EQ. 14)
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo
MV-GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but
caution must be exercised with regard to the capacitor
surge current rating. These capacitors must be capable
of handling the surge-current at power-up. The TPS
series available from AVX, and the 593D series from
Sprague are both surge current tested.
MOSFET Selection/Considerations
The ISL6420A requires 2 N-Channel power MOSFETs.
These should be selected based upon r_DS(ON), gate
supply requirements, and thermal management
requirements.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of
power dissipation for both the upper and the lower
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor (see Equations 15 and
16). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before
the synchronous rectifier turns on.
Schottky Selection
Rectifier D₂ is a clamp that catches the negative
inductor swing during the dead time between turning off
the lower MOSFET and turning on the upper MOSFET.
The diode must be a Schottky type to prevent the
parasitic MOSFET body diode from conducting. It is
acceptable to omit the diode and let the body diode of
the lower MOSFET clamp the negative inductor swing,
but efficiency will drop one or two percent as a result.
The diode's rated reverse breakdown voltage must be
greater than the maximum input voltage.
P_UFET
=
I_O2
⋅
r_DS(ON)
⋅
D
+
1_--
2
I_O
⋅
V_IN
⋅
t_sw
⋅
f_sw
(EQ. 15)
P_LFET = I_O2 ⋅ r_DS(ON) ⋅ (1 – D)
(EQ. 16)
Where D is the duty cycle = Vo/VIN, t_SW is the switching
interval, and f_SW is the switching frequency.
These equations assume linear voltage-current
transitions and do not adequately model power loss due
the reverse recovery of the lower MOSFET’s body diode.
The gate-charge losses are dissipated by the ISL6420A
and don't heat the MOSFETs. However, large
gate-charge increases the switching interval, t_SW which
increases the upper MOSFET switching losses. Ensure
that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating
the temperature rise according to package
thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power,
package type, ambient temperature and air flow.
19
FN9169.4
December 4, 2009