ISL6420A Datasheet, PDF (16/21 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6420A
VIN = 12V, V_OUT = 3.3V at 25mA LOAD
VIN
FIGURE 14. PREBIASED OUTPUT AT 25mA LOAD
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is
very important. Switching current from one power
device to another can generate voltage transients
across the impedances of the interconnecting bond
wires and circuit traces. These interconnecting
impedances should be minimized by using wide, short
printed circuit traces. The critical components should
be located as close together as possible using ground
plane construction or single point grounding.
Figure 15 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should
be part of ground or power plane in a printed circuit
board. The components shown in Figure 15 should be
located as close together as possible. Please note that
the capacitors C_IN and C_O each represent numerous
physical capacitors. Locate the ISL6420A within 3
inches of the MOSFETs, Q₁ and Q₂. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6420A must be sized to handle up to 1A peak
current.
Figure 16 shows the circuit traces that require
additional layout consideration. Use single point and
ground plane construction for the circuits shown.
Minimize any leakage current paths on the ENSS PIN
and locate the capacitor, C_ss close to the SS pin
because the internal current source is only 10µA.
Provide local V_CC decoupling between VCC and GND
pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins.
ISL6420A
UGATE
PHASE
LGATE
GND
Q1
L_O
V_OUT
Q2 D2
C_IN
C_O
RETURN
FIGURE 15. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
BOOT
D₁
C_BOOT
ISL6420A
PHASE
ENSS
+5V
C_SS
GND
V_CC
C_VCC
+VIN
Q_{1 LO}
V_OUT
Q₂ ^CO
FIGURE 16. PRINTED CIRCUIT BOARD SMALL
SIGNAL LAYOUT GUIDELINES
Feedback Compensation
Figure 17 highlights the voltage-mode control loop for
a synchronous-rectified buck converter. The output
voltage (V_OUT) is regulated to the Reference voltage
level. The error amplifier (Error Amp) output (V_E/A) is
compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated (PWM) wave with an
amplitude of VIN at the PHASE node. The PWM wave
is smoothed by the output filter (L_O and C_O).
The modulator transfer function is the small-signal
transfer function of V_OUT/V_E/A. This function is
dominated by a DC Gain and the output filter (L_O and
C_O), with a double pole break frequency at F_LC and a
zero at F_ESR. The DC Gain of the modulator is simply
the input voltage (VIN) divided by the peak-to-peak
oscillator voltage ΔV_OSC.
16
FN9169.4
December 4, 2009