ISL6420A Datasheet, PDF (14/21 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6420A
1. The maximum r_DS(ON) at the highest junction
temperature.
2. Determine I_OC for I_OC > I_OUT(MAX) + (ΔI) ⁄ 2 ,
where ΔI is the output inductor ripple current.
A small ceramic capacitor should be placed in parallel
with R_OCSET to smooth the voltage across R_OCSET in
the presence of switching noise on the input voltage.
Voltage Margining
The ISL6420A has a voltage margining mode that can
be used for system testing. The voltage margining
percentage is resistor selectable up to ±10%. The
voltage margining mode can be enabled by connecting
a margining set resistor from VMSET pin to ground and
using the control pins GPIO1/2 to toggle between
positive and negative margining (Refer to Table 2).
With voltage margining enabled, the VMSET resistor to
ground will set a current, which is switched to the FB
pin. The current will be equal to 2.468V divided by the
value of the external resistor tied to the VMSET pin.
Use a resistor in the range of 150kΩ to 400kΩ for
VMSET resistor.
I_VM
=
---²---^.--⁴---⁶----⁸---^V-----
R_VMSET
(EQ. 2)
ΔV_VM
=
2.468 V
-------^R----^F----^B--------
R_VMSET
(EQ. 3)
The power supply output increases when GPIO2 is
HIGH and decreases when GPIO1 is HIGH. The amount
that the output voltage of the power supply changes
with voltage margining, will be equal to 2.468V x the
ratio of the external feedback resistor and the external
resistor tied to VMSET. Figure 11 shows the positive
and negative margining for a 3.3V output, using a
20.5kΩ feedback resistor and using various VMSET
resistor values.
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
150 175 200 225 250 275 300 325 350 375 400
RVMSET (kΩ)
FIGURE 11. VOLTAGE MARGINING vs. VMSET
RESISTANCE
VIN = 12V, V_OUT = 3.3V, NO LOAD
FIGURE 12A.
VIN = 12V, V_OUT = 3.3V, NO LOAD
FIGURE 12B.
VIN = 12V, V_OUT = 3.3V, I_OUT = 10A
FIGURE 13. PGOOD DELAY
14
FN9169.4
December 4, 2009