ISL6420A Datasheet, PDF (13/21 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6420A
TABLE 3. VOLTAGE MARGINING CONTROLLED BY
GPIO1 AND GPIO2
GPIO1
GPIO2
VOUT
L
L
No Change
L
H
+ΔVOUT
H
L
-ΔVOUT
H
H
Ignored
Functional Description
Initialization
The ISL6420A automatically initializes upon receipt of
power. The Power-On Reset (POR) function monitors
the internal bias voltage generated from LDO output
(VCC5) and the ENSS pin. The POR function initiates
the soft-start operation after the VCC5 exceeds the
POR threshold. The POR function inhibits operation
with the chip disabled (ENSS pin <1V).
The device can operate from an input supply voltage of
5.5V to 28V connected directly to the VIN pin using the
internal 5V linear regulator to bias the chip and supply
the gate drivers. For 5V ±10% applications, connect
VIN to VCC5 to bypass the linear regulator.
Soft-Start/Enable
The ISL6420A soft-start function uses an internal
current source and an external capacitor to reduce
stresses and surge current during start-up.
When the output of the internal linear regulator
reaches the POR threshold, the POR function initiates
the soft-start sequence. An internal 10µA current
source charges an external capacitor on the ENSS pin
linearly from 0V to 3.3V.
When the ENSS pin voltage reaches 1V typically, the
internal 0.6V reference begins to charge following the
dv/dt of the ENSS voltage. As the soft-start pin
charges from 1V to 1.6V, the reference voltage charges
from 0V to 0.6V. Figure 9 shows a typical soft-start
sequence.
VIN = 28V, V_OUT = 3.3V, I_OUT = 10A
FIGURE 9. TYPICAL SOFT-START WAVEFORM
V_OUT
I_OUT
PHASE
ENSS
FIGURE 10. TYPICAL OVERCURRENT HICCUP MODE
Overcurrent Protection
The overcurrent function protects the converter from
a shorted output by using the upper MOSFET’s
ON-resistance, r_DS(ON) to monitor the current. This
method enhances the converter’s efficiency and
reduces cost by eliminating a current sensing resistor.
The overcurrent function cycles the soft-start function
in a hiccup mode to provide fault protection. A resistor
connected to the drain of the upper FET and the
OCSET pin programs the overcurrent trip level. The
PHASE node voltage will be compared against the
voltage on the OCSET pin, while the upper FET is on.
A current (100µA typically) is pulled from the OCSET
pin to establish the OCSET voltage. If PHASE is lower
than OCSET while the upper FET is on then an
overcurrent condition is detected for that clock cycle.
The upper gate pulse is immediately terminated, and
a counter is incremented. If an overcurrent condition
is detected for 8 consecutive clock cycles, and the
circuit is not in soft-start, the ISL6420A enters into
the soft-start hiccup mode. During hiccup, the
external capacitor on the ENSS pin is discharged.
After the capacitor is discharged, it is released and a
soft-start cycle is initiated. There are three dummy
soft-start delay cycles to allow the MOSFETs to cool
down, to keep the average power dissipation in hiccup
mode at an acceptable level. At the fourth soft-start
cycle, the output starts a normal soft-start cycle, and
the output tries to ramp.
During soft-start, pulse termination current limiting is
enabled, but the 8-cycle hiccup counter is held in reset
until soft-start is completed. Figure 10 shows the
overcurrent hiccup mode.
The overcurrent function will trip at a peak inductor
current (I_OC) determined from Equation 1, where
I_OCSET is the internal OCSET current source.
I_OC
=
I_{--O-----C----S----E----T-----}•_----R_{----O-----C----S----E----T--}
r_DS(ON)
(EQ. 1)
The OC trip point varies mainly due to the upper
MOSFETs r_DS(ON) variations. To avoid overcurrent
tripping in the normal operating load range, find the
R_OCSET resistor from Equation 1 with:
13
FN9169.4
December 4, 2009