ISL6420A Datasheet, PDF (17/21 Pages) Intersil Corporation – Advanced Single Synchronous Buck Pulse-Width Modulation PWM Controller

ISL6420A
VIN
OSC
DRIVER
PWM
COMPARATOR
L_O
V_OUT
ΔV_OSC
-
+
DRIVER _PHASE
C_O
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₂
C₁
R₂
Z_FB
V_OUT
Z_IN
C₃ R₃
COMP
R₁
FB
-
+
R₄
ISL6420A
REF
V_OUT
=
V_R
EF
×
⎛
⎜1
⎝
+
R-R----^14- _{⎠⎟⎞}
FIGURE 17. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
------------------¹--------------------
2π • L_O • C_O
(EQ. 4)
F_ESR=
----------------------¹----------------------
2π • (ESR • C_O)
(EQ. 5)
The compensation network consists of the error
amplifier (internal to the ISL6420A) and the
impedance networks Z_IN and Z_FB. The goal of the
compensation network is to provide a closed loop
transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase
margin is the difference between the closed loop phase
at f_0dB and 180°. The following equations relate the
compensation network’s poles, zeros and gain to the
components (R₁, R₂, R₃, C₁, C₂, and C₃) in Figure 17.
Use the following guidelines for locating the poles and
zeros of the compensation network.
Compensation Break Frequency Equations
F_Z1 = ₂----_π-----_•----_R---¹--₂-----_•----_C-----₁--
(EQ. 6)
F_P1
=
--------------------------¹----------------------------
2
π
•
R
2
•
⎛
⎝
C^-C----1^{-1----+•-----CC----2-}2^{--⎠⎞}
(EQ. 7)
F_Z2 = ₂----_π-----_•----₍---_R-----₁----+-¹----_R-----₃----₎---_•-----_C----₃--
(EQ. 8)
F_P2 = ₂----_π-----_•----_R---¹--₃-----_•----_C-----₃--
(EQ. 9)
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole
(~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop
Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 18 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator
Gain has a high gain peak due to the high Q factor of
the output filter and is not shown in Figure 18. Using
the previously mentioned guidelines should give a
Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at
F_P2 with the capabilities of the error amplifier. The Loop
Gain is constructed on the log-log graph of Figure 18
by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
100
80
60
F_Z1F_Z2 F_P1 F_P2
OPEN LOOP
ERROR AMP GAIN
40
20LOG
20 ^(R2/R1)
0
20LOG
(VIN/ΔV_OSC)
-20 MODULATOR
GAIN
-40
-60
10
100
F_LC
F_ESR
1k 10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER
GAIN
17
FN9169.4
December 4, 2009