ISL62386 Datasheet, PDF (18/20 Pages) Intersil Corporation – High-Efficiency, Quad Output System Power Supply Controller for Notebook Computers

ISL62386
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
VVIAAS TO
GGRROOUUNNDD
PLANE
ININDDUUCCTTOORR
HHIGIGHH--SSIDIDEE
MMOOSSFFEETTSS
GND
VOUT
PHASE
NODE
OUTPUT
CCAAPPAACCIITTOORRSS
SSCCHHOOTTTTKKYY
DDIIOODDEE
LLOOWW--SSIIDDEE
MMOOSSFFEETTSS
IINNPPUUTT
VIN
CCAAPPACCIITTOORRSS
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 21. This layout approach ensures
that the controller does not favor one channel over another
during critical switching decisions. Figure 30 illustrates one
example of how to achieve proper bilateral symmetry.
Co
PIN 5 (VCC)
PIN 20 (VIN)
L2
ISL62386
L2 U2
Ci
LINE OF SYMMETRY
Ci
L1 U1
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
L1
Co
FIGURE 30. SYMMETRIC LAYOUT GUIDE
Signal Ground and Power Ground
The bottom of the ISL62386 TQFN package is the signal
ground (AGND) terminal for analog and logic signals of the
IC. The bottom pad is connected to AGND1 pin and AGND2
pin internally. Connect the AGND pad of the ISL62386 to the
island of ground plane under the IC using several vias for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground (PGND) plane.
PGND (Pin 22)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 20)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 5)
For best performance, place the decoupling capacitor very
close to the VCC and AGND1 or AGND2 pin.
LDO3 (Pin 19) and LDO5 (Pin 21)
For best performance, place the decoupling capacitors very
close to LDO3 pin and PGND pin, LDO5 pin and PGND pin,
respectively, preferably on the same side of the PCB as the
ISL62386 IC.
EN (Pins 13 and 28) and PGOOD (Pin 1)
These are logic signals that are referenced to the AGND pin.
Treat them as typical logic signals.
OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30)
For DCR current sensing, current-sense network, consisting
of R_OCSET and C_SEN, needs to be connected to the
inductor pads for accurate measurement. Connect R_OCSET
to the phase-node side pad of the inductor, and connect
C_SEN to the output side pad of the inductor. The ISEN
resistor should also be connected to the output pad of the
inductor with a separate trace. Connect the OCSET pin to
the common node of node of R_OCSET and C_SEN.
For resistive current sensing, connect R_OCSET from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the V_OUT side of the resistor
pad.
In both current-sense configurations, the resistor and
capacitor sensing elements, with the exclusion of the current
sense power resistor, should be placed near the
corresponding IC pin. The trace connections to the inductor
or sensing resistor should be treated as Kelvin connections.
FB (Pins 9 and 32), and VOUT (Pins 10 and 31)
The VOUT pin is used to generate the R³ synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to
the regulation point as possible. The input impedance of the
FB pin is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and
AGND pins keeping the high impedance trace short.
FSET (Pins 2 and 8)
These pins require a quiet environment. The resistor R_FSET
and capacitor C_FSET should be placed directly adjacent to
these pins. Keep fast moving nodes away from these pins.
18
FN6831.0
February 4, 2009