ISL62386 Datasheet, PDF (12/20 Pages) Intersil Corporation – High-Efficiency, Quad Output System Power Supply Controller for Notebook Computers

ISL62386
Theory of Operation
Four Output Controller
The ISL62386 generates four regulated output voltages,
including two PWM controllers and two LDOs. The two PWM
channels are identical and almost entirely independent.
Unless otherwise stated, only one individual channel is
discussed, and the conclusion applies to both channels.
PWM Modulator
The ISL62386 modulator features Intersil’s R³ technology, a
hybrid of fixed frequency PWM control and variable
frequency hysteretic control. Intersil’s R³ technology can
simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The R³ modulator synthesizes an AC signal V_R,
which is an analog representation of the output inductor
ripple current. The duty-cycle of V_R is the result of charge
and discharge current through a ripple capacitor C_R. The
current through C_R is provided by a transconductance
amplifier g_m that measures the VIN and VO pin voltages.
The positive slope of V_R can be written as Equation 1:
V_RPOS = g_m ⋅ (V_IN – V_OUT) ⁄ C_R
(EQ. 1)
The negative slope of V_R can be written as Equation 2:
V_RNEG = g_m ⋅ V_OUT ⁄ C_R
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
RIPPLE CAPACITOR VOLTAGE V_R
WINDOW VOLTAGE V_W
(WRT V_COMP)
ERROR AMPLIFIER
VOLTAGE V_COMP
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is set by a resistor connected across the FSET and GND
pins. The V_R, V_COMP, and V_W signals feed into a window
comparator in which V_COMP is the lower threshold voltage
and V_COMP + V_W is the higher threshold voltage. Figure 23
shows PWM pulses being generated as V_R traverses the
V_COMP and V_COMP + V_W thresholds. The PWM switching
frequency is proportional to the slew rates of the positive and
negative slopes of V_R; it is inversely proportional to the
voltage between V_W and V_COMP. Equation 3 illustrates how
to calculate the window size based on output voltage and
frequency set resistor R_W.
V_W = g_m ⋅ V_OUT ⋅ (1 – D) ⋅ R_W
(EQ. 3)
Programming the PWM Switching Frequency
The ISL62386 does not use a clock signal to produce
PWMs. The PWM switching frequency F_SW is programmed
by the resistor R_W that is connected from the FSET pin to
the GND pin. The approximate PWM switching frequency
can be expressed as written in Equation 4:
F_SW
=
----------------¹----------------
10 ⋅ C_R ⋅ R_W
(EQ. 4)
For a desired F_SW, the R_W can be selected by Equation 5.
R_W
=
-----------------¹-------------------
10 ⋅ C_R ⋅ F_SW
(EQ. 5)
where C_R = 17pF with ±20% error range. To smooth the
FSET pin voltage, a ceramic capacitor such as 10nF is
necessary to parallel with R_W.
It is recommended that whenever the control loop
compensation network is modified, F_SW should be checked
for the correct frequency and if necessary, adjust R_W.
Power-On Reset
The ISL62386 is disabled until the voltage at the VIN pin has
increased above the rising power-on reset (POR) threshold
voltage. The controller will be disabled when the voltage at
the VIN pin decreases below the falling POR threshold.
In addition to VIN POR, the LDO5 pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
The ISL62386 uses a digital soft-start circuit to ramp the
output voltage of each SMPS to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pins are pulled
above their rising thresholds, the PGOOD Soft-Start Delay,
t_SS, starts and the output voltage begins to rise. The FB pin
ramps to 0.6V in approximately 1.5ms and the PGOOD pin
goes to high impedance approximately 1.25ms after the FB
pin voltage reaches 0.6V.
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. It is an undefined impedance if
V_IN is not above the rising POR threshold or below the POR
falling threshold. When a fault is detected, the ISL62386 will
turn on the open-drain NMOS, which will pull PGOOD low
with a nominal impedance of 32Ω. This will flag the system
that one of the output voltages is out of regulation.
12
FN6831.0
February 4, 2009