ISL62386 Datasheet, PDF (17/20 Pages) Intersil Corporation – High-Efficiency, Quad Output System Power Supply Controller for Notebook Computers

ISL62386
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 28 is a graph of the input capacitor
RMS ripple current, normalized relative to output load current,
as a function of duty cycle and is adjusted for converter
efficiency. The normalized RMS ripple current calculation is
written as Equation 22:
I_{C I N ( R M S ,N O R M A L I Z E D )} =
I_{--M-----A----X-----}⋅_-------D_------⋅_---(_---1_{----–-----}D_-----)_---+-----^D_--------1---^â‹---_2---^k-------²_----
I_MAX
(EQ. 22)
Where:
- I_MAX is the maximum continuous I_LOAD of the converter
- k is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I_MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
Equation 23.
D = -_V----_I-^V-_N---^O--_â‹--^U-_E----^T_F----_F---
(EQ. 23)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.48
k=1
0.36
k = 0.75
k = 0.5
k = 0.25
0.24
k=0
0.12
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE
FIGURE 28. NORMALIZED RMS INPUT CURRENT @ EFF = 1
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V_DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the
device spends the least amount of time dissipating power in
the linear region. Unlike the low-side MOSFET which has the
drain-source voltage clamped by its body diode during turn
off, the high-side MOSFET turns off with a V_DS of
approximately V_IN - V_OUT, plus the spike across it. The
preferred low-side MOSFET emphasizes low r _DS(ON) when
fully saturated to minimize conduction loss. It should be
noted that this is an optimal configuration of MOSFET
selection for low duty cycle applications (D < 50%). For
higher output, low input voltage solutions, a more balanced
MOSFET selection for high- and low-side devices may be
warranted.
For the low-side (LS) MOSFET, the power loss can be
assumed to be conductive only and is written as Equation 24:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} • (1 – D)
(EQ. 24)
For the high-side (HS) MOSFET, the conduction loss is
written as Equation 25:
P_{CON_HS}
=
I_L
O
A
2
D
•
r_D
S
(
O
N
)
_
H
S
•
D
(EQ. 25)
For the high-side MOSFET, the switching loss is written as
Equation 26:
P_{SW_HS}
=
V_{-----I--N----}•_---I_{--V----A----L---L---E----Y-----}•_--t_{--O-----N----}•_---f_--S----W---
2
+
-^V----^I--^N----^•---^I--^P----^E----^A----^K----^•---^t--^O----^F----^F----^•---^f-^S----^W----
2
(EQ. 26)
Where:
- I_VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I_PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t_ON is the time required to drive the device into
saturation
- t_OFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 27:
C_BOOT
=
---------^Q-----^g---------
ΔV_BOOT
(EQ. 27)
Where:
- Q_g is the total gate charge required to turn on the
high-side MOSFET
- ΔV_BOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q_g, of 25nC at V_GS = 5V, and a ΔV_BOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
17
FN6831.0
February 4, 2009